CLK_HW_INIT_HW
.hw.init = CLK_HW_INIT_HW(_name, _parent, \
.hw.init = CLK_HW_INIT_HW(#_var, \
.hw.init = CLK_HW_INIT_HW(#_var, \
.hw.init = CLK_HW_INIT_HW(#_var, \
ctx->parent.init = CLK_HW_INIT_HW("test-parent", &ctx->mux_ctx.hw,
ctx->hw.init = CLK_HW_INIT_HW("test-clock", &ctx->parent,
out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
.hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, _flags), \
priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div",
priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk",
priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div",
priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk",
priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div",
priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk",
.hw.init = CLK_HW_INIT_HW( \
.hw.init = CLK_HW_INIT_HW( \
.hw.init = CLK_HW_INIT_HW( \
CLK_HW_INIT_HW(#_name, &_parent.common.hw, &spacemit_ccu_ddn_ops, _flags)
_shift, _width, _flags, CLK_HW_INIT_HW)
CLK_HW_INIT_HW)
_fflag, _fvco, CLK_HW_INIT_HW)
.hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0),
.hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops,
.hw.init = CLK_HW_INIT_HW("eth2ck_k", &ck_ker_eth2.hw, &clk_stm32_gate_ops, 0),
.hw.init = CLK_HW_INIT_HW("eth2ptp_k", &ck_ker_eth2.hw, &clk_stm32_divider_ops,
.hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw,
.hw.init = CLK_HW_INIT_HW(_name, \
.hw.init = CLK_HW_INIT_HW(_name, \
.hw.init = CLK_HW_INIT_HW( \
.hw.init = CLK_HW_INIT_HW( \
.hw.init = CLK_HW_INIT_HW( \
.hw.init = CLK_HW_INIT_HW( \
.hw.init = CLK_HW_INIT_HW("c910-bus",
host_clkc->cfg_div.hw.init = CLK_HW_INIT_HW(cfg_div_name,
rtc->clk32k.init = CLK_HW_INIT_HW("clk32k", __clk_get_hw(clk),
.hw.init = CLK_HW_INIT_HW(_name, \