arch/riscv/include/asm/kvm_vcpu_pmu.h

75

int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid);

arch/riscv/kvm/tlb.c

193

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_RCVD);

arch/riscv/kvm/tlb.c

291

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD);

arch/riscv/kvm/tlb.c

300

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD);

arch/riscv/kvm/tlb.c

307

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_RCVD);

arch/riscv/kvm/tlb.c

316

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_RCVD);

arch/riscv/kvm/vcpu_exit.c

201

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_ILLEGAL_INSN);

arch/riscv/kvm/vcpu_exit.c

206

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_MISALIGNED_LOAD);

arch/riscv/kvm/vcpu_exit.c

211

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_MISALIGNED_STORE);

arch/riscv/kvm/vcpu_exit.c

216

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_ACCESS_LOAD);

arch/riscv/kvm/vcpu_exit.c

221

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_ACCESS_STORE);

arch/riscv/kvm/vcpu_sbi_replace.c

104

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_SENT);

arch/riscv/kvm/vcpu_sbi_replace.c

113

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_SENT);

arch/riscv/kvm/vcpu_sbi_replace.c

123

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_SENT);

arch/riscv/kvm/vcpu_sbi_replace.c

28

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_SET_TIMER);

arch/riscv/kvm/vcpu_sbi_replace.c

61

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_IPI_SENT);

arch/riscv/kvm/vcpu_sbi_replace.c

76

kvm_riscv_vcpu_pmu_incr_fw(tmp, SBI_PMU_FW_IPI_RCVD);