iwl_write_prph
iwl_write_prph(trans, ofs + trans->mac_cfg->umac_prph_offset, val);
iwl_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7));
iwl_write_prph(trans, SCD_TXFACT, 0);
iwl_write_prph(trans, SCD_EN_CTRL, value);
iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
iwl_write_prph(mvm->trans, mvm->dbgfs_prph_reg_addr, value);
iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
iwl_write_prph(trans, APMG_CLK_DIS_REG,
iwl_write_prph(trans, APMG_CLK_EN_REG,
iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
iwl_write_prph(trans, IMR_UREG_CHICK,
iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
iwl_write_prph(trans, addr, val);
iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
iwl_write_prph(trans,
iwl_write_prph(trans, WFPM_GP2, 0x01010101);
iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);