iwl_read32
pwrsave_status = iwl_read32(priv->trans, CSR_GP_CNTRL) &
r = iwl_read32(trans, CSR_EEPROM_REG);
u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
iwl_read32(trans, CSR_OTP_GP_REG);
otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
r = iwl_read32(trans, CSR_EEPROM_REG);
otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
iwl_read32(trans, CSR_EEPROM_GP) &
reg = iwl_read32(priv->trans, CSR_LED_REG);
ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
ev = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT);
time = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT);
data = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT);
iwl_read32(priv->trans, CSR_UCODE_DRV_GP1);
u32 scratch = iwl_read32(fwrt->trans, CSR_FUNC_SCRATCH);
u32 inta_hw = iwl_read32(trans, inta_addr);
IWL_EXPORT_SYMBOL(iwl_read32);
if ((iwl_read32(trans, addr) & mask) == (bits & mask))
u32 value = iwl_read32(trans, reg);
u32 iwl_read32(struct iwl_trans *trans, u32 ofs);
__le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,
__le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,
mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));
mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));
u32 scratch = iwl_read32(trans, CSR_FUNC_SCRATCH);
return !(iwl_read32(trans, CSR_GP_CNTRL) &
u32 val = iwl_read32(trans, CSR_IPC_STATE);
inta = iwl_read32(trans, CSR_INT);
reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
u32 val = iwl_read32(trans, CSR_IPC_STATE);
iwl_read32(trans, CSR_INT_MASK),
iwl_read32(trans, CSR_FH_INT_STATUS));
inta, iwl_read32(trans, CSR_INT_MASK));
inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
inta_hw = iwl_read32(trans, CSR_INT);
value = iwl_read32(trans, CSR_LTR_LAST_MSG);
if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
value = iwl_read32(trans, CSR_LTR_LAST_MSG);
iwl_read32(trans, CSR_FUNC_SCRATCH));
trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
val = iwl_read32(trans, CSR_RESET);
return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
vals[offs] = iwl_read32(trans,
vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
iwl_read32(trans, csr_tbl[i]));
!(iwl_read32(trans, CSR_GP_CNTRL) &
val = iwl_read32(trans_pcie->trans, CSR_HW_IF_CONFIG_REG);
val = iwl_read32(trans, CSR_HW_IF_CONFIG_REG);
info.hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID);
i, iwl_read32(trans, CSR_MONITOR_STATUS_REG));
iwl_read32(trans, CSR_RESET));
reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
*ptr = iwl_read32(trans, i);
v = iwl_read32(trans, reg);