CLK_I2C1
[CLK_I2C1] = &i2c1_clk.common.hw,
[CLK_I2C1] = &clk_i2c1.common.hw,
[CLK_I2C1] = &i2c1_clk.common.hw,
CLK_I2C1, "i2c1",
CLK_I2C1, "i2c1",
CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0),
D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8),
COMPOSITE(CLK_I2C1, "clk_i2c1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0,
GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0,
COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_bus_src", 0,
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0),
GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0),
[CLK_I2C1] = &i2c1_clk.common.hw,
static CCU_GATE(CLK_I2C1, i2c1_clk, "i2c1", perisys_apb_pclk_pd, 0x204, 4, 0);
K210_FUNC(CLK_I2C1, OUT),