CLK_I2C0
[CLK_I2C0] = &i2c0_clk.common.hw,
[CLK_I2C0] = &clk_i2c0.common.hw,
[CLK_I2C0] = &i2c0_clk.common.hw,
CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0),
D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6),
COMPOSITE(CLK_I2C0, "clk_i2c0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0,
COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_pmu200m_pmu100m_pmu50m_24m_p, 0,
COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0,
COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_bus_src", 0,
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0),
[CLK_I2C0] = &i2c0_clk.common.hw,
static CCU_GATE(CLK_I2C0, i2c0_clk, "i2c0", perisys_apb_pclk_pd, 0x204, 5, 0);