jpu
dev_err(ctx->jpu->dev, "%s field isn't supported\n",
dev_err(ctx->jpu->dev,
dev_err(ctx->jpu->dev, "incompatible or corrupted JPEG data\n");
spin_lock_irqsave(&ctx->jpu->lock, flags);
spin_unlock_irqrestore(&ctx->jpu->lock, flags);
src_vq->lock = &ctx->jpu->mutex;
src_vq->dev = ctx->jpu->v4l2_dev.dev;
dst_vq->lock = &ctx->jpu->mutex;
dst_vq->dev = ctx->jpu->v4l2_dev.dev;
struct jpu *jpu = video_drvdata(file);
ctx->jpu = jpu;
ctx->encoder = vfd == &jpu->vfd_encoder;
ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpu->m2m_dev, ctx, jpu_queue_init);
if (mutex_lock_interruptible(&jpu->mutex)) {
if (jpu->ref_count == 0) {
ret = clk_prepare_enable(jpu->clk);
ret = jpu_reset(jpu);
jpu->ref_count++;
mutex_unlock(&jpu->mutex);
clk_disable_unprepare(jpu->clk);
mutex_unlock(&jpu->mutex);
struct jpu *jpu = video_drvdata(file);
mutex_lock(&jpu->mutex);
if (--jpu->ref_count == 0)
clk_disable_unprepare(jpu->clk);
mutex_unlock(&jpu->mutex);
spin_lock_irqsave(&ctx->jpu->lock, flags);
jpu_write(ctx->jpu, JCCMD_SRST, JCCMD);
spin_unlock_irqrestore(&ctx->jpu->lock, flags);
v4l2_m2m_job_finish(ctx->jpu->m2m_dev, ctx->fh.m2m_ctx);
struct jpu *jpu = ctx->jpu;
if (jpu_wait_reset(jpu)) {
spin_lock_irqsave(&ctx->jpu->lock, flags);
jpu->curr = ctx;
jpu_write(jpu, JCMOD_DSP_ENC | JCMOD_PCTR | redu |
jpu_write(jpu, JIFECNT_SWAP_WB | inft, JIFECNT);
jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT);
jpu_write(jpu, JINTE_TRANSF_COMPL, JINTE);
jpu_write(jpu, src_1_addr, JIFESYA1);
jpu_write(jpu, src_2_addr, JIFESCA1);
jpu_write(jpu, bpl, JIFESMW);
jpu_write(jpu, (w >> 8) & JCSZ_MASK, JCHSZU);
jpu_write(jpu, w & JCSZ_MASK, JCHSZD);
jpu_write(jpu, (h >> 8) & JCSZ_MASK, JCVSZU);
jpu_write(jpu, h & JCSZ_MASK, JCVSZD);
jpu_write(jpu, w, JIFESHSZ);
jpu_write(jpu, h, JIFESVSZ);
jpu_write(jpu, dst_addr + JPU_JPEG_HDR_SIZE, JIFEDA1);
jpu_write(jpu, 0 << JCQTN_SHIFT(1) | 1 << JCQTN_SHIFT(2) |
jpu_write(jpu, 0 << JCHTN_AC_SHIFT(1) | 0 << JCHTN_DC_SHIFT(1) |
jpu_set_qtbl(jpu, ctx->compr_quality);
jpu_set_htbl(jpu);
dev_err(ctx->jpu->dev,
spin_unlock_irqrestore(&ctx->jpu->lock, flags);
jpu_write(jpu, JCMOD_DSP_DEC | JCMOD_PCTR, JCMOD);
jpu_write(jpu, JIFECNT_SWAP_WB, JIFECNT);
jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT);
jpu_write(jpu, JINTE_TRANSF_COMPL | JINTE_ERR, JINTE);
jpu_write(jpu, src_addr, JIFDSA1);
jpu_write(jpu, dst_1_addr, JIFDDYA1);
jpu_write(jpu, dst_2_addr, JIFDDCA1);
jpu_write(jpu, bpl, JIFDDMW);
jpu_write(jpu, JCCMD_JSRT, JCCMD);
spin_unlock_irqrestore(&ctx->jpu->lock, flags);
struct jpu *jpu = dev_id;
int_status = jpu_read(jpu, JINTS);
jpu_write(jpu, ~(int_status & JINTS_MASK), JINTS);
jpu_write(jpu, JCCMD_JEND, JCCMD);
spin_lock(&jpu->lock);
curr_ctx = v4l2_m2m_get_curr_priv(jpu->m2m_dev);
dev_err(jpu->dev, "no active context for m2m\n");
unsigned long payload_size = jpu_read(jpu, JCDTCU) << 16
| jpu_read(jpu, JCDTCM) << 8
| jpu_read(jpu, JCDTCD);
unsigned char error = jpu_read(jpu, JCDERR) & JCDERR_MASK;
dev_dbg(jpu->dev, "processing error: %#X: %s\n", error,
jpu->curr = NULL;
jpu_write(jpu, JCCMD_SRST, JCCMD);
spin_unlock(&jpu->lock);
v4l2_m2m_job_finish(jpu->m2m_dev, curr_ctx->fh.m2m_ctx);
spin_unlock(&jpu->lock);
struct jpu *jpu;
jpu = devm_kzalloc(&pdev->dev, sizeof(*jpu), GFP_KERNEL);
if (!jpu)
mutex_init(&jpu->mutex);
spin_lock_init(&jpu->lock);
jpu->dev = &pdev->dev;
jpu->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(jpu->regs))
return PTR_ERR(jpu->regs);
jpu->irq = ret = platform_get_irq(pdev, 0);
ret = devm_request_irq(&pdev->dev, jpu->irq, jpu_irq_handler, 0,
dev_name(&pdev->dev), jpu);
dev_err(&pdev->dev, "cannot claim IRQ %d\n", jpu->irq);
jpu->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(jpu->clk)) {
return PTR_ERR(jpu->clk);
ret = v4l2_device_register(&pdev->dev, &jpu->v4l2_dev);
jpu->m2m_dev = v4l2_m2m_init(&jpu_m2m_ops);
if (IS_ERR(jpu->m2m_dev)) {
v4l2_err(&jpu->v4l2_dev, "Failed to init mem2mem device\n");
ret = PTR_ERR(jpu->m2m_dev);
strscpy(jpu->vfd_encoder.name, DRV_NAME, sizeof(jpu->vfd_encoder.name));
jpu->vfd_encoder.fops = &jpu_fops;
jpu->vfd_encoder.ioctl_ops = &jpu_ioctl_ops;
jpu->vfd_encoder.minor = -1;
jpu->vfd_encoder.release = video_device_release_empty;
jpu->vfd_encoder.lock = &jpu->mutex;
jpu->vfd_encoder.v4l2_dev = &jpu->v4l2_dev;
jpu->vfd_encoder.vfl_dir = VFL_DIR_M2M;
jpu->vfd_encoder.device_caps = V4L2_CAP_STREAMING |
ret = video_register_device(&jpu->vfd_encoder, VFL_TYPE_VIDEO, -1);
v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n");
video_set_drvdata(&jpu->vfd_encoder, jpu);
strscpy(jpu->vfd_decoder.name, DRV_NAME, sizeof(jpu->vfd_decoder.name));
jpu->vfd_decoder.fops = &jpu_fops;
jpu->vfd_decoder.ioctl_ops = &jpu_ioctl_ops;
jpu->vfd_decoder.minor = -1;
jpu->vfd_decoder.release = video_device_release_empty;
jpu->vfd_decoder.lock = &jpu->mutex;
jpu->vfd_decoder.v4l2_dev = &jpu->v4l2_dev;
jpu->vfd_decoder.vfl_dir = VFL_DIR_M2M;
jpu->vfd_decoder.device_caps = V4L2_CAP_STREAMING |
ret = video_register_device(&jpu->vfd_decoder, VFL_TYPE_VIDEO, -1);
v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n");
video_set_drvdata(&jpu->vfd_decoder, jpu);
platform_set_drvdata(pdev, jpu);
v4l2_info(&jpu->v4l2_dev, "encoder device registered as /dev/video%d\n",
jpu->vfd_encoder.num);
v4l2_info(&jpu->v4l2_dev, "decoder device registered as /dev/video%d\n",
jpu->vfd_decoder.num);
video_unregister_device(&jpu->vfd_encoder);
v4l2_m2m_release(jpu->m2m_dev);
v4l2_device_unregister(&jpu->v4l2_dev);
struct jpu *jpu = platform_get_drvdata(pdev);
video_unregister_device(&jpu->vfd_decoder);
video_unregister_device(&jpu->vfd_encoder);
v4l2_m2m_release(jpu->m2m_dev);
v4l2_device_unregister(&jpu->v4l2_dev);
struct jpu *jpu = dev_get_drvdata(dev);
if (jpu->ref_count == 0)
clk_disable_unprepare(jpu->clk);
struct jpu *jpu = dev_get_drvdata(dev);
if (jpu->ref_count == 0)
clk_prepare_enable(jpu->clk);
struct jpu *jpu;
static u32 jpu_read(struct jpu *jpu, unsigned int reg)
return ioread32(jpu->regs + reg);
static void jpu_write(struct jpu *jpu, u32 val, unsigned int reg)
iowrite32(val, jpu->regs + reg);
static void jpu_set_tbl(struct jpu *jpu, u32 reg, const unsigned int *tbl,
jpu_write(jpu, tbl[i], reg + (i << 2));
static void jpu_set_qtbl(struct jpu *jpu, unsigned short quality)
jpu_set_tbl(jpu, JCQTBL(0), qtbl_lum[quality], QTBL_SIZE);
jpu_set_tbl(jpu, JCQTBL(1), qtbl_chr[quality], QTBL_SIZE);
static void jpu_set_htbl(struct jpu *jpu)
jpu_set_tbl(jpu, JCHTBD(0), hdctbl_lum, HDCTBL_SIZE);
jpu_set_tbl(jpu, JCHTBA(0), hactbl_lum, HACTBL_SIZE);
jpu_set_tbl(jpu, JCHTBD(1), hdctbl_chr, HDCTBL_SIZE);
jpu_set_tbl(jpu, JCHTBA(1), hactbl_chr, HACTBL_SIZE);
static int jpu_wait_reset(struct jpu *jpu)
while (jpu_read(jpu, JCCMD) & JCCMD_SRST) {
dev_err(jpu->dev, "timed out in reset\n");
static int jpu_reset(struct jpu *jpu)
jpu_write(jpu, JCCMD_SRST, JCCMD);
return jpu_wait_reset(jpu);
dev_dbg(ctx->jpu->dev, "unknown format; set default format\n");
v4l2_err(&ctx->jpu->v4l2_dev, "%s queue busy\n", __func__);
spin_lock_irqsave(&ctx->jpu->lock, flags);
spin_unlock_irqrestore(&ctx->jpu->lock, flags);
dev_err(ctx->jpu->dev, "src and dst formats do not match.\n");