drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

464

data = RREG32_DIDT(ixDIDT_DB_CTRL0);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

469

WREG32_DIDT(ixDIDT_DB_CTRL0, data);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

241

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

242

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

243

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

244

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

245

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

246

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

247

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

248

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

249

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

250

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

251

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },