iwl_write32
iwl_write32(priv->trans, CSR_GP_DRIVER_REG,
iwl_write32(trans, CSR_EEPROM_REG,
iwl_write32(trans, CSR_EEPROM_GP,
iwl_write32(trans, CSR_EEPROM_REG,
iwl_write32(priv->trans, CSR_LED_REG, CSR_LED_REG_TURN_ON);
iwl_write32(priv->trans, CSR_LED_REG,
iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
iwl_write32(priv->trans, HBUS_TARG_MEM_RADDR, ptr);
iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
iwl_write32(fwrt->trans, address + offset, value);
iwl_write32(trans, CSR_DOORBELL_VECTOR,
IWL_EXPORT_SYMBOL(iwl_write32);
iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
iwl_write32(trans, reg, value);
void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val);
iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
iwl_write32(trans, HBUS_TARG_MEM_WDAT,
iwl_write32(mvm->trans, CSR_LED_REG,
iwl_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie->iml_len);
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
iwl_write32(trans, CSR_INT_MASK, 0x00000000);
iwl_write32(trans, CSR_INT, 0xffffffff);
iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
iwl_write32(trans, HBUS_TARG_WRPTR, rxq->write_actual |
iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
iwl_write32(trans, CSR_FH_INT_STATUS,
iwl_write32(trans,
iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
iwl_write32(trans, CSR_INT_MASK, 0x00000000);
iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk);
iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
iwl_write32(trans, CSR_DOORBELL_VECTOR,
iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,
iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
iwl_write32(trans, CSR_RESET,
iwl_write32(trans, HBUS_TARG_MEM_RADDR,
iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec);
iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
iwl_write32(trans, addr, val);
iwl_write32(trans, CSR_RESET, 0);
iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16));
iwl_write32(trans, HBUS_TARG_WRPTR,
iwl_write32(trans, HBUS_TARG_WRPTR,
iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
iwl_write32(trans, reg, v);