iwl_read_prph
*val++ = cpu_to_le32(iwl_read_prph(fwrt->trans, addr + i));
IWL_EXPORT_SYMBOL(iwl_read_prph);
if ((iwl_read_prph(trans, addr) & mask) == (bits & mask))
iwl_read_prph(trans, rfh_tbl[i]));
iwl_read_prph(trans, addr));
iwl_read_prph(trans, rfh_tbl[i]));
iwl_read_prph(trans, addr));
u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs);
return iwl_read_prph(trans, ofs + trans->mac_cfg->umac_prph_offset);
data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR));
*gp2 = iwl_read_prph(mld->trans, mld->trans->mac_cfg->base->gp2_reg_addr);
iwl_read_prph(mvm->trans, mvm->dbgfs_prph_reg_addr));
iwl_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9));
iwl_read_prph(trans, SB_CPU_1_STATUS),
iwl_read_prph(trans, SB_CPU_2_STATUS));
return iwl_read_prph(mvm->trans, reg_addr);
(!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
(iwl_read_prph(trans, APMG_PS_CTRL_REG) &
version = iwl_read_prph(trans, CNVI_MBOX_C);
iwl_read_prph(trans, OSC_CLK);
iwl_read_prph(trans, OSC_CLK);
iwl_read_prph(trans, OSC_CLK);
iwl_read_prph(trans, OSC_CLK);
write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
write_ptr_val = iwl_read_prph(trans, write_ptr);
cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
cpu_to_le32(iwl_read_prph(trans, base));
cpu_to_le32(iwl_read_prph(trans, base_high));
base = (iwl_read_prph(trans, base) &
base = iwl_read_prph(trans, base) <<
cfg_reg = iwl_read_prph(trans, cfg_reg);
base = iwl_read_prph(trans, base) <<
end = iwl_read_prph(trans, end) <<
iwl_read_prph(trans, IMR_UREG_CHICK) |
val = iwl_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1);
if (iwl_read_prph(trans, addr) & BIT(val)) {
iwl_read_prph(trans, WFPM_GP2));
iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &