iris_platform_data
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
const struct iris_platform_data *iris_platform_data;
core->iris_platform_data->num_vpp_pipe;
core->iris_platform_data->num_vpp_pipe;
core->iris_platform_data->num_vpp_pipe;
for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
cp_config = &core->iris_platform_data->tz_cp_config_data[i];
extern const struct iris_platform_data qcs8300_data;
extern const struct iris_platform_data sc7280_data;
extern const struct iris_platform_data sm8250_data;
extern const struct iris_platform_data sm8550_data;
extern const struct iris_platform_data sm8650_data;
extern const struct iris_platform_data sm8750_data;
extern const struct iris_platform_data x1p42100_data;
const struct iris_platform_data sc7280_data = {
const struct iris_platform_data sm8250_data = {
const struct iris_platform_data sm8550_data = {
const struct iris_platform_data sm8650_data = {
const struct iris_platform_data sm8750_data = {
const struct iris_platform_data x1p42100_data = {
const struct iris_platform_data qcs8300_data = {
const struct vpu_ops *vpu_ops = inst->core->iris_platform_data->vpu_ops;
bw_tbl = core->iris_platform_data->bw_tbl_dec;
num_rows = core->iris_platform_data->bw_tbl_dec_size;
core->iris_platform_data->clk_rst_tbl,
core->iris_platform_data->clk_rst_tbl_size);
if (!core->iris_platform_data->controller_rst_tbl_size)
core->iris_platform_data->controller_rst_tbl,
core->iris_platform_data->controller_rst_tbl_size);
icc_tbl = core->iris_platform_data->icc_tbl;
core->iris_platform_data = of_device_get_match_data(core->dev);
core->iris_firmware_desc = core->iris_platform_data->firmware_desc;
core->icc_count = core->iris_platform_data->icc_tbl_size;
dma_mask = core->iris_platform_data->dma_mask;
.pd_names = core->iris_platform_data->pmdomain_tbl,
.num_pd_names = core->iris_platform_data->pmdomain_tbl_size,
.pd_names = core->iris_platform_data->opp_pd_tbl,
.num_pd_names = core->iris_platform_data->opp_pd_tbl_size,
.clk_names = core->iris_platform_data->opp_clk_tbl,
clk_tbl = core->iris_platform_data->clk_tbl;
clk_cnt = core->iris_platform_data->clk_tbl_size;
icc_tbl = core->iris_platform_data->icc_tbl;
if (total_mbpf > core->iris_platform_data->max_core_mbpf)
if (total_mbps > core->iris_platform_data->max_core_mbps)
caps = inst->core->iris_platform_data->inst_caps;
caps = inst->core->iris_platform_data->inst_caps;
fmt = inst->core->iris_platform_data->inst_iris_fmts;
size = inst->core->iris_platform_data->inst_iris_fmts_size;
fmt = inst->core->iris_platform_data->inst_iris_fmts;
size = inst->core->iris_platform_data->inst_iris_fmts_size;
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
caps = inst->core->iris_platform_data->inst_caps;
caps = inst->core->iris_platform_data->inst_caps;
fps = DIV_ROUND_UP(core->iris_platform_data->max_core_mbps, mbpf);
if (count < core->iris_platform_data->max_session_count)
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
u32 xo_rst_tbl_size = core->iris_platform_data->controller_rst_tbl_size;
u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {
for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
caps = inst->core->iris_platform_data->inst_caps;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
if (!core->iris_platform_data->no_aon) {
core->iris_platform_data->vpu_ops->power_off_hw(core);
core->iris_platform_data->vpu_ops->power_off_controller(core);
u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
return core->iris_platform_data->vpu_ops->set_hwmode(core);
u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
const struct vpu_ops *vpu_ops = core->iris_platform_data->vpu_ops;
ret = core->iris_platform_data->vpu_ops->power_on_controller(core);
ret = core->iris_platform_data->vpu_ops->power_on_hw(core);
core->iris_platform_data->vpu_ops->power_off_controller(core);