ivpu_dbg
ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n",
ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n",
ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n",
ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",
ivpu_dbg(vdev, PM, "NPU ready message received successfully\n");
ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n",
ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id);
ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n",
ivpu_dbg(vdev, FW_BOOT, "Preemption buffer size, primary: %u, secondary: %u\n",
ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "Mid-inference preemption %s supported\n",
ivpu_dbg(vdev, FW_BOOT, "Boot params: address 0x%llx, size %llu\n",
ivpu_dbg(vdev, FW_BOOT, "FW version: address 0x%llx, size %llu\n",
ivpu_dbg(vdev, FW_BOOT, "Runtime: address 0x%llx, size %u\n",
ivpu_dbg(vdev, FW_BOOT, "Image load offset: 0x%llx, size %u\n",
ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n",
ivpu_dbg(vdev, FW_BOOT, "FW cold boot entry point: 0x%llx\n", fw->cold_boot_entry_point);
ivpu_dbg(vdev, FW_BOOT, "SHAVE NN size: %u\n", fw->shave_nn_size);
ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_uses_ecc_mca_signal = 0x%x\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", boot_params->boot_type);
ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", boot_params->boot_type);
ivpu_dbg(vdev, FW_BOOT, "Invalid header size 0x%x\n", log->header_size);
ivpu_dbg(vdev, FW_BOOT, "Invalid log size 0x%x\n", log->size);
ivpu_dbg(vdev, FW_BOOT,
ivpu_dbg(vdev, BO, "import: bo %8p size %9zu\n", bo, ivpu_bo_size(bo));
ivpu_dbg(vdev, BO, " alloc: bo %8p size %9llu\n", bo, size);
ivpu_dbg(vdev, IOCTL, "Can't add BO %pe to ctx %u: already in ctx %u\n",
ivpu_dbg(vdev, BO,
ivpu_dbg(vdev, IOCTL, "Invalid BO flags 0x%x\n", args->flags);
ivpu_dbg(vdev, IOCTL, "Invalid BO size %llu\n", args->size);
ivpu_dbg(vdev, IOCTL, "Failed to allocate BO: %pe ctx %u size %llu flags 0x%x\n",
ivpu_dbg(vdev, IOCTL, "Failed to create handle for BO: %pe ctx %u size %llu flags 0x%x\n",
ivpu_dbg(vdev, IOCTL, "Failed to create sg table: %d\n", ret);
ivpu_dbg(vdev, IOCTL, "Failed to export userptr dma-buf: %d\n", ret);
ivpu_dbg(vdev, IOCTL, "Invalid BO flags: 0x%x\n", args->flags);
ivpu_dbg(vdev, IOCTL, "Userptr or size are zero: ptr %llx size %llu\n",
ivpu_dbg(vdev, IOCTL, "Userptr or size not page aligned: ptr %llx size %llu\n",
ivpu_dbg(vdev, IOCTL, "Userptr is not accessible: ptr %llx size %llu\n",
ivpu_dbg(vdev, IOCTL, "Failed to create handle for BO: %pe ctx %u size %llu flags 0x%x\n",
ivpu_dbg(vdev, BO, "Created userptr BO: handle=%u vpu_addr=0x%llx size=%llu flags=0x%x\n",
ivpu_dbg(vdev, IOCTL, "Failed to pin user pages: %d\n", ret);
ivpu_dbg(vdev, IOCTL, "Pinned %d pages, expected %lu\n", pinned, nr_pages);
ivpu_dbg(vdev, MISC, "MSR_INTEGRITY_CAPS: 0x%llx\n", msr_integrity_caps);
ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", platform_to_str(platform), platform);
ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config);
ivpu_dbg(vdev, PM, "Skipping workpoint request\n");
ivpu_dbg(vdev, PM, "PLL workpoint request: %lu MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n",
ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",
ivpu_dbg(vdev, IRQ, "Survivability IRQ\n");
ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",
ivpu_dbg(vdev, IRQ, "NOC Firewall interrupt detected, counter %d\n",
ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%016llx\n", func, name, reg, val);
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%08x\n", func, name, reg, val);
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%016llx\n", func, name, reg, val);
ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val);
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s started (exp_val 0x%x)\n",
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s %s (reg_val 0x%08x)\n",
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%08x\n", func, name, reg, val);
ivpu_dbg(vdev, IPC,
ivpu_dbg(vdev, JSM,
ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr);
ivpu_dbg(vdev, IOCTL, "Command queue management not supported\n");
ivpu_dbg(vdev, IOCTL, "Invalid priority %d\n", args->priority);
ivpu_dbg(vdev, IOCTL, "Command queue management not supported\n");
ivpu_dbg(vdev, JOB, "Command queue %d created, ctx %d, flags 0x%08x\n",
ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d priority %d\n",
ivpu_dbg(vdev, JOB, "DB %d unregistered\n", cmdq->db_id);
ivpu_dbg(vdev, JOB, "Command queue %d destroyed, ctx %d\n",
ivpu_dbg(vdev, IOCTL, "Failed to find command queue with ID: %u\n", cmdq_id);
ivpu_dbg(vdev, JOB, "Context ID: %u abort\n", file_priv->ctx.id);
ivpu_dbg(vdev, JOB, "Job queue full: ctx %d cmdq %d db %d head %d tail %d\n",
ivpu_dbg(vdev, JOB, "Job destroyed: id %3u ctx %2d cmdq_id %u engine %d",
ivpu_dbg(vdev, JOB, "Job created: ctx %2d engine %d", file_priv->ctx.id, job->engine_idx);
ivpu_dbg(vdev, JOB, "Job complete: id %3u ctx %2d cmdq_id %u engine %d status 0x%x\n",
ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n",
ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d cmdq_id %u engine %d prio %d addr 0x%llx next %d\n",
ivpu_dbg(vdev, IOCTL, "Failed to lookup GEM object with handle %u\n",
ivpu_dbg(vdev, IOCTL, "Buffer is already in use by another job\n");
ivpu_dbg(vdev, IOCTL, "Invalid commands offset %u for buffer size %zu\n",
ivpu_dbg(vdev, IOCTL, "Preemption buffer is too small\n");
ivpu_dbg(vdev, IOCTL, "Preemption buffer cannot be mappable\n");
ivpu_dbg(vdev, JOB, "Submit ioctl: ctx %u cmdq_id %u buf_count %u\n",
ivpu_dbg(vdev, IOCTL, "Invalid engine %d\n", args->engine);
ivpu_dbg(vdev, IOCTL, "Invalid priority %d\n", args->priority);
ivpu_dbg(vdev, IOCTL, "Invalid buffer count %u\n", args->buffer_count);
ivpu_dbg(vdev, IOCTL, "Invalid commands offset %u\n", args->commands_offset);
ivpu_dbg(vdev, IOCTL, "Context not initialized\n");
ivpu_dbg(vdev, IOCTL, "Context %u has MMU faults\n", file_priv->ctx.id);
ivpu_dbg(vdev, IOCTL, "Command queue management not supported\n");
ivpu_dbg(vdev, IOCTL, "Invalid command queue ID %u\n", args->cmdq_id);
ivpu_dbg(vdev, IOCTL, "Invalid buffer count %u\n", args->buffer_count);
ivpu_dbg(vdev, IOCTL, "Invalid preemption buffer index %u\n",
ivpu_dbg(vdev, IOCTL, "Invalid commands offset %u\n", args->commands_offset);
ivpu_dbg(vdev, IOCTL, "Context not initialized\n");
ivpu_dbg(vdev, IOCTL, "Context %u has MMU faults\n", file_priv->ctx.id);
ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref);
ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF);
ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF);
ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref);
ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size);
ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n",
ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n",
ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n",
ivpu_dbg(vdev, MMU, "CMD write: %s data: 0x%llx 0x%llx\n", name, data0, data1);
ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]);
ivpu_dbg(vdev, MMU, "CDTAB set %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",
ivpu_dbg(vdev, MMU, "Init..\n");
ivpu_dbg(vdev, MMU, "Init done\n");
ivpu_dbg(vdev, IRQ, "MMU event queue\n");
ivpu_dbg(vdev, IRQ, "MMU error\n");
ivpu_dbg(vdev, MMU_MAP, "Split 64K page ctx: %u vpu_addr: 0x%llx\n", ctx->id, vpu_addr);
ivpu_dbg(vdev, MMU_MAP, "Set read-only pages ctx: %u vpu_addr: 0x%llx size: %lu\n",
ivpu_dbg(vdev, MMU_MAP, "Map ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n",
ivpu_dbg(vdev, MMU_MAP, "Unmap ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n",
ivpu_dbg(vdev, IOCTL, "Instance doesn't exist for mask: %#llx\n",
ivpu_dbg(vdev, IOCTL, "Instance already exists (mask %#llx)\n",
ivpu_dbg(vdev, IOCTL, "Requested MS buffer size %llu exceeds range size %llu\n",
ivpu_dbg(vdev, IOCTL, "Failed to allocate MS buffer (size %llu)\n", buf_size);
ivpu_dbg(vdev, PM, "Suspend..\n");
ivpu_dbg(vdev, PM, "Suspend done.\n");
ivpu_dbg(vdev, PM, "Resume..\n");
ivpu_dbg(vdev, PM, "Resume done.\n");
ivpu_dbg(vdev, PM, "Runtime suspend..\n");
ivpu_dbg(vdev, PM, "Runtime suspend done.\n");
ivpu_dbg(vdev, PM, "Runtime resume..\n");
ivpu_dbg(vdev, PM, "Runtime resume done.\n");
ivpu_dbg(vdev, PM, "Pre-reset..\n");
ivpu_dbg(vdev, PM, "Pre-reset done.\n");
ivpu_dbg(vdev, PM, "Post-reset..\n");
ivpu_dbg(vdev, PM, "Post-reset done.\n");
ivpu_dbg(vdev, PM, "Autosuspend delay = %d\n", delay);
ivpu_dbg(vdev, PM, "DCT requested %u%% (D0: %uus, D0i2: %uus)\n",
ivpu_dbg(vdev, PM, "DCT requested to be disabled\n");
ivpu_dbg(vdev, FW_BOOT, "Cold boot entry point 0x%llx", vdev->fw->cold_boot_entry_point);
ivpu_dbg(vdev, FW_BOOT, "Warm boot entry point 0x%llx", fw->warm_boot_entry_point);