arch/powerpc/sysdev/ipic.c

530

temp = ipic_read(ipic->regs, ipic_info[src].mask);

arch/powerpc/sysdev/ipic.c

546

temp = ipic_read(ipic->regs, ipic_info[src].mask);

arch/powerpc/sysdev/ipic.c

585

temp = ipic_read(ipic->regs, ipic_info[src].mask);

arch/powerpc/sysdev/ipic.c

643

vold = ipic_read(ipic->regs, IPIC_SECNR);

arch/powerpc/sysdev/ipic.c

751

temp = ipic_read(ipic->regs, IPIC_SEMSR);

arch/powerpc/sysdev/ipic.c

783

return primary_ipic ? ipic_read(primary_ipic->regs, IPIC_SERSR) : 0;

arch/powerpc/sysdev/ipic.c

799

irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;

arch/powerpc/sysdev/ipic.c

824

ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);

arch/powerpc/sysdev/ipic.c

825

ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);

arch/powerpc/sysdev/ipic.c

826

ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);

arch/powerpc/sysdev/ipic.c

827

ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);

arch/powerpc/sysdev/ipic.c

828

ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);

arch/powerpc/sysdev/ipic.c

829

ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);

arch/powerpc/sysdev/ipic.c

830

ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);

arch/powerpc/sysdev/ipic.c

831

ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);

arch/powerpc/sysdev/ipic.c

832

ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);

arch/powerpc/sysdev/ipic.c

833

ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);

arch/powerpc/sysdev/ipic.c

834

ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);

arch/powerpc/sysdev/ipic.c

835

ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);