drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1000

ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1001

ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1003

ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1004

ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

964

ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

983

ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

984

ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

985

ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

987

ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

988

ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

989

ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

991

ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

992

ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

993

ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

995

ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

996

ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

997

ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

999

ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4],

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1729

dscl_prog_data->isharp_lba.mode = 0; // ISHARP_LBA_MODE

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1733

dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1734

dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1735

dscl_prog_data->isharp_lba.slope_seg[0] = 62; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1737

dscl_prog_data->isharp_lba.in_seg[1] = 130; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1738

dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1739

dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1741

dscl_prog_data->isharp_lba.in_seg[2] = 450; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1742

dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1743

dscl_prog_data->isharp_lba.slope_seg[2] = 0x18D; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -115

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1745

dscl_prog_data->isharp_lba.in_seg[3] = 520; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1746

dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1747

dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1749

dscl_prog_data->isharp_lba.in_seg[4] = 520; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1750

dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1751

dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1753

dscl_prog_data->isharp_lba.in_seg[5] = 520; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1754

dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1757

dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1758

dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1759

dscl_prog_data->isharp_lba.slope_seg[0] = 32; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1761

dscl_prog_data->isharp_lba.in_seg[1] = 254; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1762

dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1763

dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1765

dscl_prog_data->isharp_lba.in_seg[2] = 559; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1766

dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1767

dscl_prog_data->isharp_lba.slope_seg[2] = 0x10C; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -244

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1769

dscl_prog_data->isharp_lba.in_seg[3] = 592; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1770

dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1771

dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1773

dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1774

dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1775

dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1777

dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1778

dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1781

dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1782

dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1783

dscl_prog_data->isharp_lba.slope_seg[0] = 40; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1785

dscl_prog_data->isharp_lba.in_seg[1] = 204; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1786

dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1787

dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1789

dscl_prog_data->isharp_lba.in_seg[2] = 818; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1790

dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1791

dscl_prog_data->isharp_lba.slope_seg[2] = 0x1D9; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -39

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1793

dscl_prog_data->isharp_lba.in_seg[3] = 1023; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1794

dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1795

dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1797

dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1798

dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1799

dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1801

dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1802

dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h

402

struct isharp_lba isharp_lba; // ISHARP_LBA