iow
iow: 1; /* IO Write operation */
iow: 1; /* IO Write operation */
#define __io_pbw() RISCV_FENCE(iow, o)
wait->wait[i].iow = wait;
if (w == &w->iow->wait[IOWAIT_IB_SE]) {
iowait_set_flag(w->iow, IOWAIT_PENDING_IB);
iowait_set_flag(w->iow, IOWAIT_PENDING_TID);
w->iow->priority++;
w->iow->priority++;
w->iow->tx_count++;
w->iow->count += n;
return w->iow;
struct iowait *iow;
container_of(wait->iow, struct hfi1_ipoib_txq, wait);
iowait_queue(pkts_sent, wait->iow, &sde->dmawait);
struct rvt_qp *qp = iowait_to_qp(w->iow);
ret = wait->iow->sleep(sde, wait, tx, seq, pkts_sent);
struct rvt_qp *qp = iowait_to_qp(w->iow);
container_of(wait->iow, struct hfi1_user_sdma_pkt_q, busy);
iow(dm, DM9000_TXPLL, pkt_len);
iow(dm, DM9000_TXPLH, pkt_len >> 8);
iow(dm, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
iow(db, DM9000_RCR, 0x00); /* Stop Device */
iow(db, DM9000_ISR, int_status); /* Clear ISR status */
iow(db, DM9000_NSR, NSR_WAKEST);
iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
iow(db, DM9000_RCR, 0x00); /* Disable RX */
iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK);
iow(db, DM9000_NCR, 0);
iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK);
iow(db, DM9000_EPAR, DM9000_PHY | reg);
iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);
iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
iow(db, DM9000_EPAR, DM9000_PHY | reg);
iow(db, DM9000_EPDRL, value);
iow(db, DM9000_EPDRH, value >> 8);
iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);
iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
iow(db, DM9000_EPAR, offset);
iow(db, DM9000_EPCR, EPCR_ERPRR);
iow(db, DM9000_EPCR, 0x0);
iow(db, DM9000_EPAR, offset);
iow(db, DM9000_EPDRH, data[1]);
iow(db, DM9000_EPDRL, data[0]);
iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
iow(db, DM9000_EPCR, 0);
iow(dm, DM9000_RCSR, (features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);
iow(dm, DM9000_WCR, wcr);
iow(db, oft, dev->dev_addr[i]);
iow(db, oft++, hash_table[i]);
iow(db, oft++, hash_table[i] >> 8);
iow(db, DM9000_RCR, rcr);
iow(db, DM9000_IMR, IMR_PAR);
iow(db, DM9000_IMR, db->imr_all);
iow(db, DM9000_RCSR,
iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
iow(db, DM9000_GPR, 0);
iow(db, DM9000_NCR, ncr);
iow(db, DM9000_TCR, 0); /* TX Polling clear */
iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
iow(db, DM9000_FCR, 0xff); /* Flow Control */
iow(db, DM9000_SMCR, 0); /* Special Mode */
iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
iow(dm, DM9000_TCCR, 0);
iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP);
struct pvcalls_ioworker *iow;
iow = &map->ioworker;
queue_work(iow->wq, &iow->register_work);
struct pvcalls_ioworker *iow;
iow = &map->ioworker;
queue_work(iow->wq, &iow->register_work);
struct pvcalls_ioworker *iow;
iow = &map->ioworker;
queue_work(iow->wq, &iow->register_work);