CLK_GATE_PARENT
CLK_GATE_PARENT("ocrama", OCRAMA_IPG, "axi"),
CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),
CLK_GATE_PARENT("dsp", DSP_ROOT, "axi"),
CLK_GATE_PARENT("dspdbg", DSPDBG_ROOT, "axi"),
CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),