irqstat
u32 irqstat = read_sysreg(ICC_IAR1);
return irqstat;
u64 irqstat;
irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
return irqstat;
u64 irqstat, apr;
irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
return irqstat;
*per_cpu_ptr(desc->kstat_irqs, cpuid) = (struct irqstat) { };
return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
card->irqstat[15]++;
card->irqstat[14]++;
card->irqstat[12]++;
card->irqstat[11]++;
card->irqstat[5]++;
card->irqstat[1]++;
card->irqstat[6]++;
card->irqstat[4]++;
card->irqstat[10]++;
card->irqstat[2]++;
card->irqstat[3]++;
card->irqstat[7]++;
card->irqstat[8]++;
unsigned long irqstat[16];
u32 irqstat;
irqstat = readl_relaxed(mpic->per_cpu + MPIC_CPU_INTACK);
i = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat);
u32 irqstat;
irqstat = irq_reg_readl(gc, AT91_AIC_ISR);
if (!irqstat)
u32 irqstat;
irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR);
if (!irqstat)
u32 irqstat;
irqstat = readw_relaxed(clps711x_intc->intmr[0]) &
if (irqstat)
fls(irqstat) - 1);
irqstat = readw_relaxed(clps711x_intc->intmr[1]) &
if (irqstat)
fls(irqstat) - 1 + 16);
} while (irqstat);
u32 irqstat, irqnr;
irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
irqnr = irqstat & GICC_IAR_INT_ID_MASK;
writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
this_cpu_write(sgi_intid, irqstat);
u32 irqstat, irqnr;
irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
irqnr = irqstat & GICC_IAR_INT_ID_MASK;
unsigned long irqstat;
irqstat = readl_relaxed(data->regs + CHANIPR(idx));
for_each_set_bit(pos, &irqstat, 32)
unsigned int i, irqstat, event;
regmap_read(ltc3589->regmap, LTC3589_IRQSTAT, &irqstat);
if (irqstat & LTC3589_IRQSTAT_THERMAL_WARN) {
if (irqstat & LTC3589_IRQSTAT_UNDERVOLT_WARN) {
unsigned int i, irqstat, event;
regmap_read(ltc3676->regmap, LTC3676_IRQSTAT, &irqstat);
dev_dbg(dev, "irq%d irqstat=0x%02x\n", irq, irqstat);
if (irqstat & LTC3676_IRQSTAT_THERMAL_WARN) {
if (irqstat & LTC3676_IRQSTAT_UNDERVOLT_WARN) {
u8 irqstat;
irqstat = CMOS_READ(RTC_INTR_FLAGS);
irqstat = (unsigned long)irq & 0xF0;
irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF;
irqstat &= (cmos_rtc.suspend_ctrl & RTC_IRQMASK) | RTC_IRQF;
if (irqstat & RTC_AIE) {
if (is_intr(irqstat)) {
rtc_update_irq(p, 1, irqstat);
unsigned char irqstat;
twl_rtc->irqstat = twl_rtc->rtc_irq_bits;
set_rtc_irq_bit(twl_rtc, twl_rtc->irqstat);
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);
u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);
__raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */
__raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
u32 irqstat;
irqstat = mcspi_read_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS);
if (!irqstat)
if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
unsigned int irqstat;
irqstat = bcm_uart_readl(port, UART_IR_REG);
if (irqstat & UART_RX_INT_STAT)
if (irqstat & UART_TX_INT_STAT)
if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
u16 irqstat;
irqstat = isp116x_read_reg16(isp116x, HCuPINT);
isp116x_write_reg16(isp116x, HCuPINT, irqstat);
if (irqstat & (HCuPINT_ATL | HCuPINT_SOF)) {
if (irqstat & HCuPINT_OPR) {
irqstat &= ~HCuPINT_OPR;
if (irqstat & (HCuPINT_ATL | HCuPINT_SOF)) {
u8 irqstat;
irqstat = sl811_read(sl811, SL11H_IRQ_STATUS);
if (irqstat & SL11H_INTMASK_INSRMV)
irqstat &= ~SL11H_INTMASK_RD;
sl811_write(sl811, SL11H_IRQ_STATUS, irqstat);
if (irqstat & SL11H_INTMASK_RD) {
if (irqstat & SL11H_INTMASK_DP)
u8 irqstat = 0;
irqstat |= SL11H_INTMASK_DONE_A;
irqstat |= SL11H_INTMASK_DONE_A;
return irqstat;
u8 irqstat;
irqstat = sl811_read(sl811, SL11H_IRQ_STATUS) & ~SL11H_INTMASK_DP;
if (irqstat) {
sl811_write(sl811, SL11H_IRQ_STATUS, irqstat);
irqstat &= sl811->irq_enable;
if (irqstat == 0) {
irqstat = checkdone(sl811);
if (irqstat)
if (irqstat & SL11H_INTMASK_DONE_A) {
if (irqstat & SL11H_INTMASK_DONE_B) {
if (irqstat & SL11H_INTMASK_SOFINTR) {
if (irqstat & SL11H_INTMASK_INSRMV) {
if (irqstat & SL11H_INTMASK_RD)
} else if (irqstat & SL11H_INTMASK_RD) {
irqstat &= ~SL11H_INTMASK_RD;
if (irqstat) {
struct irqstat __percpu *kstat_irqs;
u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
desc->kstat_irqs = alloc_percpu(struct irqstat);
*per_cpu_ptr(desc->kstat_irqs, cpu) = (struct irqstat) { };
uint64_t irqstat;
irqstat = gic_common_ops->gic_read_iar();
intid = irqstat & GENMASK(23, 0);
uint64_t irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
return irqstat;