irq_mask_all
u32 irq_mask_all = 0;
irq_mask_all |= dmc520_irq_configs[idx].mask;
if (!irq_mask_all) {
dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
dmc520_write_reg(pvt, irq_mask_all, REG_OFFSET_INTERRUPT_CLR);
if (irq_mask_all & DRAM_ECC_INT_CE_BIT)
if (irq_mask_all & DRAM_ECC_INT_UE_BIT)
dmc520_write_reg(pvt, reg_val | irq_mask_all,
u32 reg_val, idx, irq_mask_all = 0;
dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
irq_mask_all |= pvt->masks[idx];
iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);