drivers/edac/dmc520_edac.c

482

u32 irq_mask_all = 0;

drivers/edac/dmc520_edac.c

495

irq_mask_all |= dmc520_irq_configs[idx].mask;

drivers/edac/dmc520_edac.c

500

if (!irq_mask_all) {

drivers/edac/dmc520_edac.c

553

dmc520_write_reg(pvt, reg_val & (~irq_mask_all),

drivers/edac/dmc520_edac.c

555

dmc520_write_reg(pvt, irq_mask_all, REG_OFFSET_INTERRUPT_CLR);

drivers/edac/dmc520_edac.c

573

if (irq_mask_all & DRAM_ECC_INT_CE_BIT)

drivers/edac/dmc520_edac.c

576

if (irq_mask_all & DRAM_ECC_INT_UE_BIT)

drivers/edac/dmc520_edac.c

587

dmc520_write_reg(pvt, reg_val | irq_mask_all,

drivers/edac/dmc520_edac.c

605

u32 reg_val, idx, irq_mask_all = 0;

drivers/edac/dmc520_edac.c

614

dmc520_write_reg(pvt, reg_val & (~irq_mask_all),

drivers/edac/dmc520_edac.c

620

irq_mask_all |= pvt->masks[idx];

drivers/net/ethernet/intel/e100.c

627

iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);