irq_init
((vpe)->funcs->irq_init ? (vpe)->funcs->irq_init((vpe)) : 0)
int (*irq_init)(struct amdgpu_vpe *vpe);
.irq_init = vpe_v6_1_irq_init,
irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
irq_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask,
irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
irq_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables);
irq_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked);
irq_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, de_hpd_enables);
irq_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, de_hpd_enables);
irq_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
int (*irq_init)(struct mt6397_chip *chip);
.irq_init = mt6397_irq_init,
.irq_init = mt6397_irq_init,
.irq_init = mt6358_irq_init,
.irq_init = mt6397_irq_init,
.irq_init = mt6358_irq_init,
.irq_init = mt6358_irq_init,
.irq_init = mt6397_irq_init,
ret = pmic_core->irq_init(pmic);