CLK_ENABLE_REG_16BIT
[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
else if (clk->flags & CLK_ENABLE_REG_16BIT)
else if (clk->flags & CLK_ENABLE_REG_16BIT)
else if (clk->flags & CLK_ENABLE_REG_16BIT)
SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
CLK_ENABLE_REG_16BIT | \