arch/sh/kernel/cpu/sh2a/clock-sh7264.c

82

[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

84

[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

110

[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

112

[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT

drivers/sh/clk/cpg.c

23

else if (clk->flags & CLK_ENABLE_REG_16BIT)

drivers/sh/clk/cpg.c

36

else if (clk->flags & CLK_ENABLE_REG_16BIT)

drivers/sh/clk/cpg.c

46

else if (clk->flags & CLK_ENABLE_REG_16BIT)

include/linux/sh_clk.h

133

SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)

include/linux/sh_clk.h

77

CLK_ENABLE_REG_16BIT | \