Symbol: CLK_ENABLE_ON_INIT
arch/sh/kernel/cpu/clock-cpg.c
10
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/clock-cpg.c
16
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/clock-cpg.c
21
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/clock-cpg.c
26
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
54
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
83
| CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
111
| CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
113
| CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
50
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
65
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
80
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
109
[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
110
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
111
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
112
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
113
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
139
[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
140
[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
141
[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
142
[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
143
[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
176
[MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
180
[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
181
[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
59
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
78
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
112
[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
113
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
114
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
115
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
116
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
142
[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
143
[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
144
[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
145
[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
146
[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
174
[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
178
[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
179
[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
59
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
81
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
114
[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
115
[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
116
[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
117
[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
118
[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
142
[HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
143
[HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
62
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
84
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
115
[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
116
[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
117
[DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
118
[DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
119
[DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
143
[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
144
[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
145
[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
146
[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
147
[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
148
[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
149
[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
151
[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
178
[HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
63
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
85
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
154
[DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
155
[DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
156
[DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
158
[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
194
[DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
203
[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
204
[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
205
[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
206
[HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
207
[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
208
[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
209
[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
210
[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
212
[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
68
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
87
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
45
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
73
[DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
74
[DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
75
[DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
76
[DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
77
[DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
78
[DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
40
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
70
[DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
71
[DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
72
[DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7763.c
79
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7780.c
85
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
43
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
73
[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
74
[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
75
[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
76
[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
77
[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
45
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
73
[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
74
[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
75
[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
76
[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
39
.flags = CLK_ENABLE_ON_INIT,
arch/sh/kernel/cpu/sh4a/clock-shx3.c
67
[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
68
[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
69
[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
70
[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
drivers/sh/clk/core.c
467
if (clkp->flags & CLK_ENABLE_ON_INIT)
drivers/sh/clk/cpg.c
350
if (parent->flags & CLK_ENABLE_ON_INIT)