CLK_ENABLE
bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE;
DUMPREG(CLK_ENABLE);
sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |