irq_bits
int irq_bits;
irq_bits = 32;
irq_bits = 64;
irq_bits = 32;
irq_bits = 32;
irq_bits = 32;
irq_bits = 32;
irq_bits = 64;
irq_bits = 64;
if (irq_bits == 32) {
if (board->irq_bits) {
(1 << it->options[1]) & board->irq_bits) {
unsigned int irq_bits;
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
.irq_bits = 0x000c,
.irq_bits = 0x000c,
.irq_bits = 0x000c,
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
.irq_bits = 0xdcfc,
bits = irq_bits(config->ibirq);
cb7210_write_byte(cb_priv, irq_bits(cb_priv->irq), HS_INT_LEVEL);
cb7210_write_byte(cb_priv, irq_bits(cb_priv->irq), HS_INT_LEVEL);
cb7210_write_byte(cb_priv, irq_bits(cb_priv->irq), HS_INT_LEVEL);
unsigned long irq_bits;
irq_bits = irq_status;
for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
for_each_set_bit(i, &irq_bits, TQMX86_NGPI)
static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u8 irq_bits)
writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
status, !(status & irq_bits), 1,
adpt->netdev->name, status, irq_bits);
static void f_ospi_enable_irq_status(struct f_ospi *ospi, u32 irq_bits)
val |= irq_bits;
static void f_ospi_disable_irq_status(struct f_ospi *ospi, u32 irq_bits)
val &= ~irq_bits;
static void f_ospi_disable_irq_output(struct f_ospi *ospi, u32 irq_bits)
val &= ~irq_bits;
ia_css_rx_get_irq_info(unsigned int *irq_bits);
ia_css_rx_port_get_irq_info(enum mipi_port_id port, unsigned int *irq_bits);
ia_css_rx_clear_irq_info(unsigned int irq_bits);
ia_css_rx_port_clear_irq_info(enum mipi_port_id port, unsigned int irq_bits);
extern void omap_disable_dma_irq(int ch, u16 irq_bits);
static const u8 irq_bits[] = { 2, 3, 4, 1 };
val = irq_bits[pos] << 3;
int cfg, irq_bits, dma, dma_bits, tmp, tmp1;
irq_bits = irqs[chip->irq & 0x0f];
if (irq_bits < 0) {
irq_bits = 0;
snd_es1688_write(chip, 0xb1, cfg | (irq_bits << 2));
unsigned char irq_bits;
irq_bits = 0x05;
irq_bits = 0x01;
irq_bits = 0x02;
irq_bits = 0x03;
irq_bits = 0x04;
outb(irq_bits << 3 | dma_bits, chip->wss_base);
unsigned char irq_bits;
irq_bits = 0x05;
irq_bits = 0x01;
irq_bits = 0x02;
irq_bits = 0x03;
irq_bits = 0x04;
outb(irq_bits << 3 | dma_bits, chip->wss_base);
snd_opti9xx_write(chip, OPTi9XX_MC_REG(3), (irq_bits << 3 | dma_bits));