irq_alloc_descs
ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
irqbase = irq_alloc_descs(-1, 0, 8, -1);
ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
r = irq_alloc_descs(OCTEON_IRQ_WDOG0, OCTEON_IRQ_WDOG0, 16, -1);
WARN(irq_alloc_descs(I8259A_IRQ_BASE, I8259A_IRQ_BASE,
irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
irq_base = irq_alloc_descs(SE7724_FPGA_IRQ_BASE, SE7724_FPGA_IRQ_BASE,
irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1);
irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
trig->subirq_base = irq_alloc_descs(-1, 0,
err = irq_alloc_descs(-1, 0, ARRAY_SIZE(clps711x_irqs), numa_node_id());
irq_base = irq_alloc_descs(-1, 0, num_irqs, 0);
irq_base = irq_alloc_descs(-1, 0, nr_irqs, numa_node_id());
ret = irq_alloc_descs(-1, min_irq, dom_sz - min_irq,
irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
chip->irq_base = irq_alloc_descs(irq_base, 0, nr_irqs, 0);
chip->irq_base = irq_alloc_descs(-1, 0, MAX8925_NR_IRQS, 0);
new_irq_base = irq_alloc_descs(irq_base, 0, irq_num, -1);
irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1);
irq_base = irq_alloc_descs(pdata->irq_base, 0,
irq_alloc_descs(irq_base, 0, ARRAY_SIZE(wm8350_irqs), 0);
irq = irq_alloc_descs(-1, 0, nvec, -1);
irq_alloc_descs(-1, 1, 1, node)
irq_alloc_descs(at, at, 1, node)
irq_alloc_descs(-1, from, 1, node)
irq_alloc_descs(-1, from, cnt, node)
if (irq_alloc_descs(info->virq_base, info->virq_base, info->size,