iris_platform_data
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
buffers->size = inst->core->iris_platform_data->get_vpu_buffer_size(inst, buffer_type);
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
u32 hw_response_timeout_val = core->iris_platform_data->hw_response_timeout;
const struct iris_platform_data *iris_platform_data;
caps = core->iris_platform_data->inst_fw_caps_dec;
num_cap = core->iris_platform_data->inst_fw_caps_dec_size;
core->iris_platform_data->num_vpp_pipe;
core->iris_platform_data->num_vpp_pipe;
core->iris_platform_data->num_vpp_pipe;
caps = core->iris_platform_data->inst_fw_caps_enc;
num_cap = core->iris_platform_data->inst_fw_caps_enc_size;
return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
u32 pas_id = core->iris_platform_data->pas_id;
fwpath = core->iris_platform_data->fwname;
ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id);
for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
cp_config = &core->iris_platform_data->tz_cp_config_data[i];
qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
config_params = core->iris_platform_data->dec_input_config_params_default;
config_params_size = core->iris_platform_data->dec_input_config_params_default_size;
config_params = core->iris_platform_data->enc_input_config_params;
config_params_size = core->iris_platform_data->enc_input_config_params_size;
bufsz.size = inst->core->iris_platform_data->get_vpu_buffer_size(inst, BUF_DPB);
subcribe_prop = core->iris_platform_data->dec_input_prop;
subcribe_prop = core->iris_platform_data->dec_output_prop_avc;
core->iris_platform_data->dec_output_prop_avc_size;
subcribe_prop = core->iris_platform_data->dec_output_prop_hevc;
core->iris_platform_data->dec_output_prop_hevc_size;
subcribe_prop = core->iris_platform_data->dec_output_prop_vp9;
core->iris_platform_data->dec_output_prop_vp9_size;
subcribe_prop = core->iris_platform_data->dec_output_prop_av1;
core->iris_platform_data->dec_output_prop_av1_size;
caps = core->iris_platform_data->inst_caps;
const struct iris_platform_data *pdata = inst->core->iris_platform_data;
change_param = core->iris_platform_data->dec_input_config_params_default;
core->iris_platform_data->dec_input_config_params_default_size;
change_param = core->iris_platform_data->dec_input_config_params_hevc;
core->iris_platform_data->dec_input_config_params_hevc_size;
change_param = core->iris_platform_data->dec_input_config_params_vp9;
core->iris_platform_data->dec_input_config_params_vp9_size;
change_param = core->iris_platform_data->dec_input_config_params_av1;
core->iris_platform_data->dec_input_config_params_av1_size;
subscribe_prop_size = core->iris_platform_data->dec_input_prop_size;
payload = core->iris_platform_data->ubwc_config->max_channels;
payload = core->iris_platform_data->ubwc_config->mal_length;
payload = core->iris_platform_data->ubwc_config->highest_bank_bit;
payload = core->iris_platform_data->ubwc_config->bank_swzl_level;
payload = core->iris_platform_data->ubwc_config->bank_swz2_level;
payload = core->iris_platform_data->ubwc_config->bank_swz3_level;
payload = core->iris_platform_data->ubwc_config->bank_spreading;
extern const struct iris_platform_data qcs8300_data;
extern const struct iris_platform_data sc7280_data;
extern const struct iris_platform_data sm8250_data;
extern const struct iris_platform_data sm8550_data;
extern const struct iris_platform_data sm8650_data;
extern const struct iris_platform_data sm8750_data;
const struct iris_platform_data sm8250_data = {
const struct iris_platform_data sc7280_data = {
const struct iris_platform_data sm8650_data = {
const struct iris_platform_data sm8750_data = {
const struct iris_platform_data qcs8300_data = {
const struct iris_platform_data sm8550_data = {
const struct vpu_ops *vpu_ops = inst->core->iris_platform_data->vpu_ops;
bw_tbl = core->iris_platform_data->bw_tbl_dec;
num_rows = core->iris_platform_data->bw_tbl_dec_size;
core->iris_platform_data->clk_rst_tbl,
core->iris_platform_data->clk_rst_tbl_size);
if (!core->iris_platform_data->controller_rst_tbl_size)
core->iris_platform_data->controller_rst_tbl,
core->iris_platform_data->controller_rst_tbl_size);
icc_tbl = core->iris_platform_data->icc_tbl;
core->iris_platform_data = of_device_get_match_data(core->dev);
core->icc_count = core->iris_platform_data->icc_tbl_size;
core->iris_platform_data->init_hfi_command_ops(core);
core->iris_platform_data->init_hfi_response_ops(core);
dma_mask = core->iris_platform_data->dma_mask;
.pd_names = core->iris_platform_data->pmdomain_tbl,
.num_pd_names = core->iris_platform_data->pmdomain_tbl_size,
.pd_names = core->iris_platform_data->opp_pd_tbl,
.num_pd_names = core->iris_platform_data->opp_pd_tbl_size,
.clk_names = core->iris_platform_data->opp_clk_tbl,
clk_tbl = core->iris_platform_data->clk_tbl;
clk_cnt = core->iris_platform_data->clk_tbl_size;
icc_tbl = core->iris_platform_data->icc_tbl;
if (total_mbpf > core->iris_platform_data->max_core_mbpf)
if (total_mbps > core->iris_platform_data->max_core_mbps)
hw_response_timeout_val = core->iris_platform_data->hw_response_timeout;
caps = inst->core->iris_platform_data->inst_caps;
caps = inst->core->iris_platform_data->inst_caps;
fmt = inst->core->iris_platform_data->inst_iris_fmts;
size = inst->core->iris_platform_data->inst_iris_fmts_size;
fmt = inst->core->iris_platform_data->inst_iris_fmts;
size = inst->core->iris_platform_data->inst_iris_fmts_size;
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
inst = core->iris_platform_data->get_instance();
const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
caps = inst->core->iris_platform_data->inst_caps;
caps = inst->core->iris_platform_data->inst_caps;
fps = DIV_ROUND_UP(core->iris_platform_data->max_core_mbps, mbpf);
if (count < core->iris_platform_data->max_session_count)
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
u32 xo_rst_tbl_size = core->iris_platform_data->controller_rst_tbl_size;
u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {
for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
caps = inst->core->iris_platform_data->inst_caps;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
if (!core->iris_platform_data->no_aon) {
core->iris_platform_data->vpu_ops->power_off_hw(core);
core->iris_platform_data->vpu_ops->power_off_controller(core);
u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
ret = core->iris_platform_data->vpu_ops->power_on_controller(core);
ret = core->iris_platform_data->vpu_ops->power_on_hw(core);
const struct vpu_ops *vpu_ops = core->iris_platform_data->vpu_ops;
core->iris_platform_data->set_preset_registers(core);
core->iris_platform_data->vpu_ops->power_off_controller(core);
value = (u32)core->sfr_daddr + core->iris_platform_data->core_arch;