io_read
struct read_cache *rc = &ctxt->io_read;
ctxt->io_read.pos = 0;
ctxt->io_read.end = 0;
struct read_cache *r = &ctxt->io_read;
struct read_cache io_read;
lsb = io_read(state, ADV748X_IO_CHIP_REV_ID_1);
msb = io_read(state, ADV748X_IO_CHIP_REV_ID_2);
#define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) | (v))
bool rgb_output = io_read(sd, 0x02) & 0x02;
if (hdmi_signal && (io_read(sd, 0x60) & 1))
if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
return io_read(sd, 0x0c) & 0x24;
return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
return io_read(sd, 0x12) & 0x01;
stdi->interlaced = io_read(sd, 0x12) & 0x10;
if (hdmi_signal && (io_read(sd, 0x60) & 1))
cec_irq = io_read(sd, info->cec_irq_status) & 0x0f;
const u8 irq_reg_0x43 = io_read(sd, 0x43);
const u8 irq_reg_0x6b = io_read(sd, 0x6b);
const u8 irq_reg_0x70 = io_read(sd, 0x70);
(io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
(io_read(sd, 0x01) & 0x70) >> 4);
ret = io_read(sd, 0x02);
bool audio_mute = io_read(sd, 0x65) & 0x40;
return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
u8 value = io_read(sd, 0x6f);
u8 value = io_read(sd, 0x6f);
u8 value = io_read(sd, 0x6f);
bool rgb_output = io_read(sd, 0x02) & 0x02;
if (hdmi_signal && (io_read(sd, 0x60) & 1))
if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
return io_read(sd, 0x0c) & 0x24;
if (io_read(sd, 0x0c) & 0x24)
if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
cec_irq = io_read(sd, 0x93) & 0x0f;
irq_status[0] = io_read(sd, 0x43);
irq_status[1] = io_read(sd, 0x57);
irq_status[2] = io_read(sd, 0x70);
irq_status[3] = io_read(sd, 0x75);
irq_status[4] = io_read(sd, 0x9d);
irq_status[5] = io_read(sd, 0x66);
(io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
if (!(io_read(sd, 0x60) & cri->present_mask)) {
io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
u8 reg_io_0x02 = io_read(sd, 0x02);
u8 reg_io_0x21 = io_read(sd, 0x21);
bool audio_mute = io_read(sd, 0x65) & 0x40;
io_read(sd, 0x6f) & 0x02 ? "true" : "false");
(io_read(sd, 0x6a) & 0x02) ? "true" : "false");
(io_read(sd, 0x6a) & 0x20) ? "true" : "false");
io_read(sd, 0x6f) & 0x01 ? "true" : "false");
(io_read(sd, 0x6a) & 0x01) ? "true" : "false");
(io_read(sd, 0x6a) & 0x10) ? "true" : "false");
io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
(io_read(sd, 0x01) & 0x70) >> 4);
cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1);
return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
u8 reg = io_read(sd, 0x6f);
reg->val = io_read(sd, reg->reg & 0xff);
reg = io_read(sd, REG_HDMI_INFO_RST);
reg = io_read(sd, REG_INT_FLG_CLR_MODE);
reg = io_read(sd, REG_RATE_CTRL);
reg = io_read(sd, REG_OF);
reg = io_read(sd, REG_OF);
u8 reg = io_read(sd, REG_DETECT_5V);
u8 reg = io_read(sd, REG_DETECT_5V);
vfront1 = io_read(sd, REG_FMT_V_FRONT_F1);
vfront2 = io_read(sd, REG_FMT_V_FRONT_F2);
vsync = io_read(sd, REG_FMT_V_SYNC);
vback1 = io_read(sd, REG_FMT_V_BACK_F1);
vback2 = io_read(sd, REG_FMT_V_BACK_F2);
reg = io_read(sd, REG_MODE_REC_CFG1);
reg = io_read(sd, REG_MODE_REC_CFG1);
reg = io_read(sd, REG_CLK_A_STATUS);
reg = io_read(sd, REG_CLK_B_STATUS);
reg = io_read(sd, REG_SUS_STATUS);
reg = io_read(sd, REG_PIX_REPEAT);
reg = io_read(sd, REG_PIX_REPEAT);
source = io_read(sd, REG_INT_FLG_CLR_SUS);
reg = io_read(sd, REG_HDMI_INFO_RST);
reg = io_read(sd, REG_SUS_STATUS);
reg = io_read(sd, REG_SUS_STATUS);
source = io_read(sd, REG_INT_FLG_CLR_DDC);
source = io_read(sd, REG_INT_FLG_CLR_RATE);
reg = io_read(sd, REG_INT_FLG_CLR_RATE);
reg = io_read(sd, REG_PIX_REPEAT);
source = io_read(sd, REG_INT_FLG_CLR_INFO);
source = io_read(sd, REG_INT_FLG_CLR_AUDIO);
reg = io_read(sd, REG_SUS_STATUS);
reg = io_read(sd, REG_HDMI_INFO_RST);
reg = io_read(sd, REG_AUDIO_FREQ);
reg = io_read(sd, REG_AUDIO_FLAGS);
source = io_read(sd, REG_INT_FLG_CLR_HDCP);
reg = io_read(sd, REG_INT_MASK_TOP);
flags = io_read(sd, REG_INT_FLG_CLR_TOP);
reg = io_read(sd, REG_VERSION);
reg = io_read(sd, REG_CMTP_REG10);
reg = io_read(sd, REG_VDP_CTRL);
state->hdmi_status = io_read(sd, REG_HDMI_FLAGS);
reg = io_read(sd, REG_CMTP_REG10);
state->chip_revision = io_read(sd, REG_CMTP_REG11);
ret = 0x34 + ((io_read(sd, REG_SLAVE_ADDR)>>4) & 0x03);
val = io_read(sd, reg);
val = io_read(sd, reg + 1);
val = io_read(sd, reg);
val = io_read(sd, reg + 1);
val = io_read(sd, reg + 2);
val = io_read(sd, reg + i);
hpd_auto = io_read(sd, REG_HPD_AUTO_CTRL);
hpd_pwr = io_read(sd, REG_HPD_POWER);
hpd_man = io_read(sd, REG_HPD_MAN_CTRL);
reg = io_read(sd, REG_VDP_CTRL);
reg = io_read(sd, REG_VDP_CTRL);
reg = io_read(sd, REG_VDP_CTRL);
buf[i] = priv->io_read(priv);
priv->io_read = gpio_nand_io_read;
if (!priv->io_read || !priv->io_write) {
u8 (*io_read)(struct gpio_nand *this);
u32 (*io_read)(struct netxen_adapter *, void __iomem *);
(adapter->io_read(adapter, addr))
adapter->io_read = netxen_nic_io_read_128M,
adapter->io_read = netxen_nic_io_read_2M,
DEFINE_EVENT(io_data, io_read,
.issue = io_read,
.issue = io_read,
.issue = io_read,
return io_read(req, issue_flags);
int io_read(struct io_kiocb *req, unsigned int issue_flags);