CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0
CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0,
CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),