ipu_cm_write
ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
ipu_cm_write(ipu, val, IPU_DISP_GEN);
ipu_cm_write(ipu, val, IPU_CONF);
ipu_cm_write(ipu, val, IPU_CONF);
ipu_cm_write(ipu, val, IPU_DISP_GEN);
ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
ipu_cm_write(ipu, idma_mask(channel->num),
ipu_cm_write(ipu, val, IPU_SRM_PRI2);
ipu_cm_write(ipu, idma_mask(channel->num),
ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
ipu_cm_write(ipu, val, IPU_CONF);
ipu_cm_write(ipu, val, IPU_CONF);
ipu_cm_write(ipu, src_reg, link->src.reg);
ipu_cm_write(ipu, sink_reg, link->sink.reg);
ipu_cm_write(ipu, src_reg, link->src.reg);
ipu_cm_write(ipu, sink_reg, link->sink.reg);