drivers/gpu/drm/i915/display/hsw_ips.c

42

intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL,

drivers/gpu/drm/i915/display/hsw_ips.c

75

intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL, 0));

drivers/gpu/drm/i915/display/intel_cdclk.c

1224

intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

2304

ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,

drivers/gpu/drm/i915/display/intel_cdclk.c

891

ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);

drivers/gpu/drm/i915/display/intel_cdclk.c

921

intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,

drivers/gpu/drm/i915/display/intel_display_power.c

1263

if (intel_parent_pcode_write(display, GEN6_PCODE_WRITE_D_COMP, val))

drivers/gpu/drm/i915/display/intel_display_power_well.c

570

ret = intel_parent_pcode_write(display, ICL_PCODE_EXIT_TCCOLD, 0);

drivers/gpu/drm/i915/display/intel_hdcp.c

409

ret = intel_parent_pcode_write(display, SKL_PCODE_LOAD_HDCP_KEYS, 1);

drivers/gpu/drm/i915/display/intel_parent.h

118

int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val);

drivers/gpu/drm/i915/display/skl_watermark.c

186

ret = intel_parent_pcode_write(display, GEN9_PCODE_SAGV_CONTROL,