arch/powerpc/include/asm/ipic.h

72

extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);

arch/powerpc/sysdev/ipic.c

29

static struct ipic * primary_ipic;

arch/powerpc/sysdev/ipic.c

516

static inline struct ipic * ipic_from_irq(unsigned int virq)

arch/powerpc/sysdev/ipic.c

523

struct ipic *ipic = ipic_from_irq(d->irq);

arch/powerpc/sysdev/ipic.c

530

temp = ipic_read(ipic->regs, ipic_info[src].mask);

arch/powerpc/sysdev/ipic.c

532

ipic_write(ipic->regs, ipic_info[src].mask, temp);

arch/powerpc/sysdev/ipic.c

539

struct ipic *ipic = ipic_from_irq(d->irq);

arch/powerpc/sysdev/ipic.c

546

temp = ipic_read(ipic->regs, ipic_info[src].mask);

arch/powerpc/sysdev/ipic.c

548

ipic_write(ipic->regs, ipic_info[src].mask, temp);

arch/powerpc/sysdev/ipic.c

559

struct ipic *ipic = ipic_from_irq(d->irq);

arch/powerpc/sysdev/ipic.c

567

ipic_write(ipic->regs, ipic_info[src].ack, temp);

arch/powerpc/sysdev/ipic.c

578

struct ipic *ipic = ipic_from_irq(d->irq);

arch/powerpc/sysdev/ipic.c

585

temp = ipic_read(ipic->regs, ipic_info[src].mask);

arch/powerpc/sysdev/ipic.c

587

ipic_write(ipic->regs, ipic_info[src].mask, temp);

arch/powerpc/sysdev/ipic.c

590

ipic_write(ipic->regs, ipic_info[src].ack, temp);

arch/powerpc/sysdev/ipic.c

601

struct ipic *ipic = ipic_from_irq(d->irq);

arch/powerpc/sysdev/ipic.c

643

vold = ipic_read(ipic->regs, IPIC_SECNR);

arch/powerpc/sysdev/ipic.c

650

ipic_write(ipic->regs, IPIC_SECNR, vnew);

arch/powerpc/sysdev/ipic.c

683

struct ipic *ipic = h->host_data;

arch/powerpc/sysdev/ipic.c

685

irq_set_chip_data(virq, ipic);

arch/powerpc/sysdev/ipic.c

700

struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)

arch/powerpc/sysdev/ipic.c

702

struct ipic *ipic;

arch/powerpc/sysdev/ipic.c

710

ipic = kzalloc_obj(*ipic);

arch/powerpc/sysdev/ipic.c

711

if (ipic == NULL)

arch/powerpc/sysdev/ipic.c

714

ipic->irqhost = irq_domain_create_linear(of_fwnode_handle(node),

arch/powerpc/sysdev/ipic.c

716

&ipic_host_ops, ipic);

arch/powerpc/sysdev/ipic.c

717

if (ipic->irqhost == NULL) {

arch/powerpc/sysdev/ipic.c

718

kfree(ipic);

arch/powerpc/sysdev/ipic.c

722

ipic->regs = ioremap(res.start, resource_size(&res));

arch/powerpc/sysdev/ipic.c

725

ipic_write(ipic->regs, IPIC_SICNR, 0x0);

arch/powerpc/sysdev/ipic.c

742

ipic_write(ipic->regs, IPIC_SICFR, temp);

arch/powerpc/sysdev/ipic.c

748

ipic_write(ipic->regs, IPIC_SERCR, temp);

arch/powerpc/sysdev/ipic.c

751

temp = ipic_read(ipic->regs, IPIC_SEMSR);

arch/powerpc/sysdev/ipic.c

758

ipic_write(ipic->regs, IPIC_SEMSR, temp);

arch/powerpc/sysdev/ipic.c

760

primary_ipic = ipic;

arch/powerpc/sysdev/ipic.c

763

ipic_write(ipic->regs, IPIC_SIMSR_H, 0);

arch/powerpc/sysdev/ipic.c

764

ipic_write(ipic->regs, IPIC_SIMSR_L, 0);

arch/powerpc/sysdev/ipic.c

768

return ipic;

arch/powerpc/sysdev/ipic.c

822

struct ipic *ipic = primary_ipic;

arch/powerpc/sysdev/ipic.c

824

ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);

arch/powerpc/sysdev/ipic.c

825

ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);

arch/powerpc/sysdev/ipic.c

826

ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);

arch/powerpc/sysdev/ipic.c

827

ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);

arch/powerpc/sysdev/ipic.c

828

ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);

arch/powerpc/sysdev/ipic.c

829

ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);

arch/powerpc/sysdev/ipic.c

830

ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);

arch/powerpc/sysdev/ipic.c

831

ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);

arch/powerpc/sysdev/ipic.c

832

ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);

arch/powerpc/sysdev/ipic.c

833

ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);

arch/powerpc/sysdev/ipic.c

834

ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);

arch/powerpc/sysdev/ipic.c

835

ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);

arch/powerpc/sysdev/ipic.c

842

ipic_write(ipic->regs, IPIC_SIMSR_H, 0);

arch/powerpc/sysdev/ipic.c

843

ipic_write(ipic->regs, IPIC_SIMSR_L, 0);

arch/powerpc/sysdev/ipic.c

844

ipic_write(ipic->regs, IPIC_SEMSR, 0);

arch/powerpc/sysdev/ipic.c

845

ipic_write(ipic->regs, IPIC_SERMR, 0);

arch/powerpc/sysdev/ipic.c

853

struct ipic *ipic = primary_ipic;

arch/powerpc/sysdev/ipic.c

855

ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);

arch/powerpc/sysdev/ipic.c

856

ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);

arch/powerpc/sysdev/ipic.c

857

ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);

arch/powerpc/sysdev/ipic.c

858

ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);

arch/powerpc/sysdev/ipic.c

859

ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);

arch/powerpc/sysdev/ipic.c

860

ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);

arch/powerpc/sysdev/ipic.c

861

ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);

arch/powerpc/sysdev/ipic.c

862

ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);

arch/powerpc/sysdev/ipic.c

863

ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);

arch/powerpc/sysdev/ipic.c

864

ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);

arch/powerpc/sysdev/ipic.c

865

ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);

arch/powerpc/sysdev/ipic.c

866

ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);