ipg
clk_set_parent(clk[cko_sel], clk[ipg]);
clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
struct clk *ipg;
ipg = of_clk_get_by_name(np, "ipg");
if (IS_ERR(ipg)) {
ret = clk_prepare_enable(ipg);
clk_put(ipg);
u32 ipg;
ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
ipg |= 0x50 << 8; /* ifg enforce 0x50 */
writel(ipg, ¯egs->ipg);
u32 ipg; /* 0x5008 */
ipg_data->ipg = DEFAULT_IPG;
ipg_data->ipg = MIN_IPG - IPG_STEP;
ipg_data->ipg = ipg_data->current_ipg;
tmp_ipg = ipg_data->ipg;
lp->ipg_data.ipg = DEFAULT_IPG;
unsigned int ipg;
int ipg;
ipg = (adap->params.rev == T3_REV_C) ? 0 : 1;
V_TXFIFOTHRESH(thres) | V_TXIPG(ipg));
u32 ipg[NTX_SCHED];
&hw_sched_buff->ipg[i], true);
unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
if (ipg) {
*ipg = (10000 * v) / core_ticks_per_usec(adap);
value = (ANA_POL_MODE_CFG_IPG_SIZE(ipg) |
u8 ipg = 20;
ipg = min_t(u8, GENMASK(4, 0), conf->ipg);
u8 ipg; /* Size of IPG when MSCC_QOS_RATE_MODE_LINE is chosen */
u32 ipg;
ipg = emac->is_sr1 ? MII_RT_TX_IPG_1G_SR1 : MII_RT_TX_IPG_1G;
ipg = emac->is_sr1 ? MII_RT_TX_IPG_100M_SR1 : MII_RT_TX_IPG_100M;
ipg = MII_RT_TX_IPG_100M;
icssg_mii_update_ipg(prueth->mii_rt, slice, ipg);
void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg)
regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, ipg);
regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG1, ipg);
void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg);
mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode)
if (ipg < sig_ext + slot_time + sifs)
ipg = 0;
if (!ipg)
ipg -= sig_ext;
if (ipg <= (TM_MAX_SIFS + slot_time)) {
sifs = ipg - slot_time;
u32 val = (ipg + slot_time) / slot_time;
ipg -= ((1 << cw) - 1) * slot_time;
aifsn = ipg / slot_time;
ipg -= aifsn * slot_time;
if (ipg > TM_DEFAULT_SIFS)
sifs = min_t(u32, ipg, TM_MAX_SIFS);
u32 ipg = td->tx_ipg;
if (duty_cycle && tx_time && !ipg) {
ipg = tx_time * 100 / duty_cycle - tx_time;
} else if (duty_cycle && !tx_time && ipg) {
tx_time = duty_cycle * ipg / (100 - duty_cycle);
mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
if (ipg)
td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
priv->ipg = devm_clk_get_enabled(dev, "ipg");
if (IS_ERR(priv->ipg))
return dev_err_probe(dev, PTR_ERR(priv->ipg),
struct clk *ipg;
u8 ipg;
u8 ipg;
u8 ipg;
u8 ipg;
u8 ipg[0x4];
mqs_priv->ipg = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(mqs_priv->ipg)) {
PTR_ERR(mqs_priv->ipg));
return PTR_ERR(mqs_priv->ipg);
ret = clk_prepare_enable(mqs_priv->ipg);
clk_disable_unprepare(mqs_priv->ipg);
clk_disable_unprepare(mqs_priv->ipg);
struct clk *ipg;
rpmsg->ipg = devm_clk_get_optional(&pdev->dev, "ipg");
if (IS_ERR(rpmsg->ipg))
return PTR_ERR(rpmsg->ipg);
ret = clk_prepare_enable(rpmsg->ipg);
clk_disable_unprepare(rpmsg->ipg);
clk_disable_unprepare(rpmsg->ipg);
struct clk *ipg;