CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH
mout_cmu_mux_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,