CLK_CON_MUX_CLK_CPUCL_PLL
CLK_CON_MUX_CLK_CPUCL_PLL,
CLK_CON_MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
CLK_CON_MUX_CLK_CPUCL_PLL,
mout_clk_cpucl_pll0_p, CLK_CON_MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),