integrated_info
kfree(bp->base.integrated_info);
struct integrated_info *info)
struct integrated_info *info)
struct integrated_info *info)
static struct integrated_info *bios_parser_create_integrated_info(
struct integrated_info *info;
info = kzalloc_obj(struct integrated_info);
bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
if (bp->base.integrated_info) {
DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
bp->base.integrated_info->gpuclk_ss_percentage;
bp->base.integrated_info->gpuclk_ss_type;
struct integrated_info *info)
struct integrated_info *info)
struct integrated_info *info)
struct integrated_info *info)
static struct integrated_info *bios_parser_create_integrated_info(
struct integrated_info *info;
info = kzalloc_obj(struct integrated_info);
bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
kfree(bp->base.integrated_info);
if (bp->integrated_info)
clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
if (bp->integrated_info)
clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
if (ctx->dc_bios->integrated_info &&
ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
ctx->dc_bios->integrated_info) {
rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info &&
ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
if (ctx->dc_bios->integrated_info) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info &&
ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
if (ctx->dc_bios->integrated_info) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info &&
ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info &&
ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
if (ctx->dc_bios->integrated_info) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info &&
ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
if (ctx->dc_bios->integrated_info) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info &&
ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
ctx->dc_bios->integrated_info,
if (ctx->dc_bios->integrated_info) {
clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq;
dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type;
dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4;
dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 2;
if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) {
if (ctx->dc_bios->integrated_info) {
clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq;
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
dcn42b_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type;
dcn42b_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4;
dcn42b_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 2;
struct integrated_info *integrated_info;
if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) {
if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings))
const struct integrated_info *info,
if (bios->integrated_info) {
&bios->integrated_info->ext_disp_conn_info.path[i];
(bios->integrated_info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
((bios->integrated_info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
if (link->ctx->dc_bios->integrated_info)
link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control;