ioread64
REMAP1(u64, ioread64, const)
extern u64 ioread64(const void __iomem *);
ret = IO_CONCAT(__IO_PREFIX,ioread64)(addr);
#define ioread64 ioread64
#define ioread64be(p) swab64(ioread64(p))
#define ioread64 ioread64
IO_CONCAT(__IO_PREFIX,ioread64)(const void __iomem *a)
ret = IO_CONCAT(__IO_PREFIX,ioread64)(addr);
EXPORT_SYMBOL(ioread64);
extern u64 ioread64(const void __iomem *addr);
#define ioread64 ioread64
EXPORT_SYMBOL(ioread64);
return ioread64(reg);
return ioread64(chip->regs + reg);
#define fsl_ioread64(p) ioread64(p)
status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset);
group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset);
group->grpcfg.flags.bits = ioread64(idxd->reg_base + grpcfg_offset);
ioread64(idxd->reg_base + grpcfg_offset));
grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
ioread64(idxd->reg_base + grpcfg_offset));
offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
idxd->hw.dsacap0.bits = ioread64(idxd->reg_base + IDXD_DSACAP0_OFFSET);
idxd->hw.dsacap1.bits = ioread64(idxd->reg_base + IDXD_DSACAP1_OFFSET);
idxd->hw.dsacap2.bits = ioread64(idxd->reg_base + IDXD_DSACAP2_OFFSET);
idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET);
evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
idxd->sw_err.bits[i] = ioread64(idxd->reg_base +
hwc->config_base = ioread64(CNTRCFG_REG(idxd, idx));
hwc->event_base = ioread64(CNTRCFG_REG(idxd, idx));
event->hw.event_base = ioread64(PERFMON_TABLE_OFFSET(idxd));
return ioread64(CNTRDATA_REG(idxd, cntr));
cntrdata = ioread64(CNTRDATA_REG(idxd, cntr));
cntr_cfg = ioread64(CNTRCFG_REG(idxd, cntr));
perfcap.bits = ioread64(PERFCAP_REG(idxd));
return ioread64(pvr_dev->regs + reg);
return ioread64(ggtt->gsm + (offset / XE_PAGE_SIZE));
#ifdef ioread64
return ioread64(reg);
bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET);
bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 2));
u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4));
u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 2));
u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4));
u.v64 = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
u.v64 = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
u.v64 = ioread64(mmio + XEON_PBAR23LMT_OFFSET);
u.v64 = ioread64(mmio + XEON_PBAR45LMT_OFFSET);
u.v64 = ioread64(mmio + XEON_SBAR0BASE_OFFSET);
u.v64 = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
u.v64 = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
base = ioread64(mmio + base_reg) & NTB_BAR_MASK_64;
reg_val = ioread64(mmio + xlat_reg);
reg_val = ioread64(mmio + limit_reg);
bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
u.v64 = ioread64(mmio + GEN3_IMBAR1XBASE_OFFSET);
u.v64 = ioread64(mmio + GEN3_IMBAR2XBASE_OFFSET);
u.v64 = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
u.v64 = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
u.v64 = ioread64(mmio + GEN3_EMBAR1XBASE_OFFSET);
u.v64 = ioread64(mmio + GEN3_EMBAR2XBASE_OFFSET);
u.v64 = ioread64(mmio + GEN3_EMBAR1XLMT_OFFSET);
u.v64 = ioread64(mmio + GEN3_EMBAR2XLMT_OFFSET);
u.v64 = ioread64(mmio + GEN3_EMBAR0_OFFSET);
u.v64 = ioread64(mmio + GEN3_EMBAR1_OFFSET);
u.v64 = ioread64(mmio + GEN3_EMBAR2_OFFSET);
reg_val = ioread64(mmio + xlat_reg);
reg_val = ioread64(mmio + limit_reg);
base = ioread64(mmio + GEN3_EMBAR1_OFFSET + (8 * idx));
reg_val = ioread64(mmio + limit_reg);
return ioread64(mmio);
bar_addr = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
bar_addr = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
u.v64 = ioread64(mmio + GEN4_IM23XBASE_OFFSET);
u.v64 = ioread64(mmio + GEN4_IM45XBASE_OFFSET);
u.v64 = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
u.v64 = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
reg_val = ioread64(mmio + xlat_reg);
reg_val = ioread64(mmio + limit_reg);
bar_addr = ioread64(&mmio_pff->pci_bar64[i]);
u64 msg = ioread64(&sndev->mmio_self_dbmsg->imsg[i]);
size = ioread64(&sndev->peer_shared->mw_sizes[widx]);
u64 peer = ioread64(&sndev->peer_shared->magic);
ret = ioread64(&sndev->mmio_self_dbmsg->idb) >> sndev->db_shift;
part_map = ioread64(&sndev->mmio_ntb->ep_map);
s->part_bitmap = ioread64(&stdev->mmio_sw_event->part_event_bitmap);
#define vfio_ioread64 ioread64
#ifndef ioread64
#define ioread64 ioread64
#ifndef ioread64
#ifndef ioread64
#ifdef ioread64