arch/parisc/include/asm/asmregs.h

131

ior: .reg %cr21

arch/parisc/include/asm/elf.h

285

dst[46] = pt->isr; dst[47] = pt->ior; \

arch/parisc/include/asm/kgdb.h

41

unsigned long ior;

arch/parisc/include/uapi/asm/ptrace.h

38

unsigned long ior; /* CR21 */

arch/parisc/include/uapi/asm/ptrace.h

59

unsigned long ior; /* CR21 */

arch/parisc/kernel/asm-offsets.c

134

DEFINE(TASK_PT_IOR, offsetof(struct task_struct, thread.regs.ior));

arch/parisc/kernel/asm-offsets.c

219

DEFINE(PT_IOR, offsetof(struct pt_regs, ior));

arch/parisc/kernel/kgdb.c

115

regs->ior = gr->ior;

arch/parisc/kernel/kgdb.c

84

gr->ior = regs->ior;

arch/parisc/kernel/perf_regs.c

27

return regs->ior;

arch/parisc/kernel/ptrace.c

457

case RI(ior): return regs->ior;

arch/parisc/kernel/ptrace.c

510

case RI(ior): return regs->ior;

arch/parisc/kernel/ptrace.c

723

REG_OFFSET_NAME(ior),

arch/parisc/kernel/toc.c

38

regs->ior = (unsigned long)toc->cr[21];

arch/parisc/kernel/toc.c

61

regs->ior = toc->cr[21];

arch/parisc/kernel/traps.c

152

level, regs->iir, regs->isr, regs->ior);

arch/parisc/kernel/traps.c

378

regs->ior = pim_wide->cr[21];

arch/parisc/kernel/traps.c

402

regs->ior = pim_narrow->cr[21];

arch/parisc/kernel/traps.c

663

fault_address = regs->ior;

arch/parisc/kernel/traps.c

677

fault_address = regs->ior;

arch/parisc/kernel/traps.c

744

((void __user *) regs->ior));

arch/parisc/kernel/traps.c

759

(void __user *)regs->ior);

arch/parisc/kernel/traps.c

775

(void __user *)regs->ior);

arch/parisc/kernel/unaligned.c

113

unsigned long saddr = regs->ior;

arch/parisc/kernel/unaligned.c

118

regs->isr, regs->ior, toreg);

arch/parisc/kernel/unaligned.c

141

unsigned long saddr = regs->ior;

arch/parisc/kernel/unaligned.c

146

regs->isr, regs->ior, toreg);

arch/parisc/kernel/unaligned.c

174

unsigned long saddr = regs->ior;

arch/parisc/kernel/unaligned.c

180

regs->isr, regs->ior, toreg);

arch/parisc/kernel/unaligned.c

239

val, regs->isr, regs->ior);

arch/parisc/kernel/unaligned.c

250

: "r" (val), "r" (regs->ior), "r" (regs->isr) );

arch/parisc/kernel/unaligned.c

268

val, regs->isr, regs->ior);

arch/parisc/kernel/unaligned.c

291

: "r" (val), "r" (regs->ior), "r" (regs->isr)

arch/parisc/kernel/unaligned.c

309

val, regs->isr, regs->ior);

arch/parisc/kernel/unaligned.c

337

: "r" (val), "r" (regs->ior), "r" (regs->isr)

arch/parisc/kernel/unaligned.c

366

: "r" (val), "r" (regs->ior), "r" (regs->isr)

arch/parisc/kernel/unaligned.c

382

perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->ior);

arch/parisc/kernel/unaligned.c

394

current->comm, task_pid_nr(current), regs->ior,

arch/parisc/kernel/unaligned.c

410

regs->ior, (void *)regs->iaoq[0], regs->iir);

arch/parisc/kernel/unaligned.c

618

(void __user *)regs->ior);

arch/parisc/kernel/unaligned.c

625

(void __user *)regs->ior);

arch/parisc/kernel/unaligned.c

681

return (int)(regs->ior & align_mask);

arch/parisc/mm/fault.c

495

address = regs->ior;

arch/riscv/include/asm/io.h

55

#define __io_par(v) RISCV_FENCE(i, ior)

drivers/counter/104-quad-8.c

1214

flg_pins = u8_get_bits(priv->ior[channel], FLG_PINS);

drivers/counter/104-quad-8.c

1271

priv->ior[channel] = SELECT_IOR | DISABLE_AB | u8_encode_bits(LOAD_CNTR, LOAD_PIN) |

drivers/counter/104-quad-8.c

1273

ret = regmap_write(priv->map, QUAD8_CONTROL(channel), priv->ior[channel]);

drivers/counter/104-quad-8.c

456

if (u8_get_bits(priv->ior[count->id], LOAD_PIN) == LOAD_CNTR)

drivers/counter/104-quad-8.c

539

if (flg_pins == u8_get_bits(priv->ior[event_node->channel], FLG_PINS))

drivers/counter/104-quad-8.c

543

ret = quad8_control_register_update(priv->map, priv->ior, event_node->channel,

drivers/counter/104-quad-8.c

63

u8 ior[QUAD8_NUM_COUNTERS];

drivers/counter/104-quad-8.c

774

*enable = u8_get_bits(priv->ior[count->id], AB_GATE);

drivers/counter/104-quad-8.c

788

ret = quad8_control_register_update(priv->map, priv->ior, count->id, enable, AB_GATE);

drivers/counter/104-quad-8.c

905

*preset_enable = !u8_get_bits(priv->ior[count->id], LOAD_PIN);

drivers/counter/104-quad-8.c

921

ret = quad8_control_register_update(priv->map, priv->ior, count->id, !preset_enable,

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

123

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

139

list_for_each_entry(ior, &disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

140

if (ior->func->power)

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

141

ior->func->power(ior, true, true, true, true, true);

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

174

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

203

ior = list_first_entry(&disp->iors, typeof(*ior), head);

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

204

nvkm_ior_del(&ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

135

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

136

struct nvkm_bios *bios = ior->disp->engine.subdev.device->bios;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

144

for (i = 0; i < ior->dp.nr; i++) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

181

ior->func->dp->drive(ior, i, ocfg.pc, ocfg.dc, ocfg.pe, ocfg.tx_pu);

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

210

outp->ior->func->dp->pattern(outp->ior, pattern);

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

262

for (i = 0; i < lt->outp->ior->dp.nr && eq_done; i++) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

293

for (i = 0; i < lt->outp->ior->dp.nr; i++) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

315

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

324

OUTP_DBG(outp, "training %dx%02x", ior->dp.nr, ior->dp.bw);

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

327

sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

328

sink[1] = ior->dp.nr;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

329

if (ior->dp.ef)

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

371

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

378

OUTP_DBG(outp, "programming link for %dx%02x", ior->dp.nr, ior->dp.bw);

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

388

while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

394

init.or = ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

395

init.link = ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

402

while ((ior->dp.bw * 2700) < nvbios_rd16(bios, lnkcmp))

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

406

while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

413

init.or = ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

414

init.link = ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

418

ret = ior->func->dp->links(ior, outp->dp.aux);

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

427

ior->func->dp->power(ior, ior->dp.nr);

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

439

init.or = outp->ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

440

init.link = outp->ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

451

init.or = outp->ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

452

init.link = outp->ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

457

init.or = outp->ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

458

init.link = outp->ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

466

init.or = outp->ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

467

init.link = outp->ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

489

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

493

if (outp->dp.rate[rate].rate == (retrain ? ior->dp.bw : outp->dp.lt.bw) * 27000)

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

511

ior->dp.mst = outp->dp.lt.mst;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

512

ior->dp.ef = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

513

ior->dp.bw = outp->dp.lt.bw;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

514

ior->dp.nr = outp->dp.lt.nr;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

529

nvkm_dp_disable(struct nvkm_outp *outp, struct nvkm_ior *ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

532

nvbios_init(&ior->disp->engine.subdev, outp->dp.info.script[4],

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

534

init.or = ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

535

init.link = ior->arm.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

542

outp->ior->dp.nr = 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

543

nvkm_dp_disable(outp, outp->ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

33

g84_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

35

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

56

g84_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

58

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

79

g84_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey)

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

81

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

175

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

179

list_for_each_entry(ior, &disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

180

if (ior->type != SOR)

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

183

clksor = nvkm_rd32(device, 0x614300 + nv50_ior_base(ior));

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

205

gf119_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

207

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

231

gf119_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

233

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

253

gf119_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

255

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

37

gf119_sor_hda_device_entry(struct nvkm_ior *ior, int head)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

39

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

46

gf119_sor_hda_eld(struct nvkm_ior *ior, int head, u8 *data, u8 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

48

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

49

const u32 soff = 0x030 * ior->id + (head * 0x04);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

60

gf119_sor_hda_hpd(struct nvkm_ior *ior, int head, bool present)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

62

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

63

const u32 soff = 0x030 * ior->id + (head * 0x04);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

68

ior->func->hda->device_entry(ior, head);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

33

gk104_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

35

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

54

gk104_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

56

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

77

gk104_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

79

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

103

const u32 sor = ior ? ior->id + 1 : 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

104

u32 link = ior ? (ior->asy.link == 2) : 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

71

gm200_sor_hdmi_scdc(struct nvkm_ior *ior, u32 khz, bool support, bool scrambling,

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

74

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

75

const u32 soff = nv50_ior_base(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

78

ior->tmds.high_speed = khz > 340000;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

81

if (ior->tmds.high_speed)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

83

if (ior->tmds.high_speed || scrambling_low_rates)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

99

gm200_sor_route_set(struct nvkm_outp *outp, struct nvkm_ior *ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

100

const u32 soff = nv50_ior_base(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

119

gt215_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

121

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

123

const u32 soff = nv50_ior_base(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

141

gt215_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

143

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

148

const u32 soff = nv50_ior_base(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

186

gt215_sor_bl_set(struct nvkm_ior *ior, int lvl)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

188

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

189

const u32 soff = nv50_ior_base(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

201

gt215_sor_bl_get(struct nvkm_ior *ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

203

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

204

const u32 soff = nv50_ior_base(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

35

gt215_sor_hda_eld(struct nvkm_ior *ior, int head, u8 *data, u8 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

37

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

38

const u32 soff = ior->id * 0x800;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

49

gt215_sor_hda_hpd(struct nvkm_ior *ior, int head, bool present)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

51

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

58

nvkm_mask(device, 0x61c448 + ior->id * 0x800, mask, data);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

96

gt215_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

98

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

100

gv100_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

102

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

124

gv100_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

126

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

146

gv100_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

148

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

38

gv100_sor_hda_device_entry(struct nvkm_ior *ior, int head)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

40

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

36

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

37

list_for_each_entry(ior, &disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

38

if (ior->type == type && (id < 0 || ior->id == id))

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

39

return ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

47

struct nvkm_ior *ior = *pior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

48

if (ior) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

49

IOR_DBG(ior, "dtor");

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

50

list_del(&ior->head);

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

60

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

61

if (!(ior = kzalloc_obj(*ior)))

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

63

ior->func = func;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

64

ior->disp = disp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

65

ior->type = type;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

66

ior->id = id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

67

ior->hda = hda;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

68

snprintf(ior->name, sizeof(ior->name), "%s-%d", nvkm_ior_name[ior->type], ior->id);

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

69

list_add_tail(&ior->head, &disp->iors);

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c

70

IOR_DBG(ior, "ctor");

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h

111

nv50_ior_base(struct nvkm_ior *ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h

113

return ior->id * 0x800;

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h

125

nv50_sor_link(struct nvkm_ior *ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h

127

return nv50_ior_base(ior) + ((ior->asy.link == 2) * 0x80);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

100

struct nvkm_head *head = nvkm_head_find(ior->disp, __ffs(state->head));

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1030

struct nvkm_ior *ior, int id, u32 khz)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1034

struct nvkm_outp *outp = ior->asy.outp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1041

IOR_DBG(ior, "nothing to attach");

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1051

if (ior->type == SOR) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1052

if (ior->asy.proto == LVDS) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1056

if (ior->asy.link == 3)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1060

data = nvbios_ocfg_match(bios, data, ior->asy.proto_evo, flags,

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1064

ior->asy.proto_evo, flags);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1072

id, ior->asy.proto_evo, flags, khz);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1078

init.or = ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1079

init.link = ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1085

nv50_disp_super_ied_off(struct nvkm_head *head, struct nvkm_ior *ior, int id)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1087

struct nvkm_outp *outp = ior->arm.outp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1093

IOR_DBG(ior, "nothing attached");

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1103

init.or = ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1104

init.link = ior->arm.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1112

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1113

list_for_each_entry(ior, &head->disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1114

if (ior->asy.head & (1 << head->id)) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1115

HEAD_DBG(head, "to %s", ior->name);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1116

return ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1126

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1127

list_for_each_entry(ior, &head->disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1128

if (ior->arm.head & (1 << head->id)) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1129

HEAD_DBG(head, "on %s", ior->name);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1130

return ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1140

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1144

ior = nv50_disp_super_ior_asy(head);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1145

if (!ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1149

nv50_disp_super_ied_on(head, ior, 1, head->asy.hz / 1000);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1152

if (ior->func->war_3)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1153

ior->func->war_3(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1157

nv50_disp_super_2_2_dp(struct nvkm_head *head, struct nvkm_ior *ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1161

const u32 linkKBps = ior->dp.bw * 27000;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1173

h = h - (3 * ior->dp.ef) - (12 / ior->dp.nr);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1179

v = v - ((36 / ior->dp.nr) + 3) - 1;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1181

ior->func->dp->audio_sym(ior, head->id, h, v);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1184

link_data_rate = (khz * head->asy.or.depth / 8) / ior->dp.nr;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1190

for (TU = 64; ior->func->dp->activesym && TU >= 32; TU--) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1241

if (ior->func->dp->activesym) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1247

ior->func->dp->activesym(ior, head->id, bestTU, bestVTUa, bestVTUf, bestVTUi);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1259

ior->func->dp->watermark(ior, head->id, unk);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1267

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1271

ior = nv50_disp_super_ior_asy(head);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1272

if (!ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1275

outp = ior->asy.outp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1286

if (outp && ior->type == SOR && ior->asy.proto == LVDS) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1288

ior->asy.link = outp->lvds.dual ? 3 : 1;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1292

nv50_disp_super_ied_on(head, ior, 0, khz);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1295

head->func->rgclk(head, ior->asy.rgdiv);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1298

if (ior->type == SOR && ior->asy.proto == DP)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1299

nv50_disp_super_2_2_dp(head, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1302

ior->func->clock(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1303

if (ior->func->war_2)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1304

ior->func->war_2(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1320

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1324

ior = nv50_disp_super_ior_arm(head);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1325

if (!ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1329

nv50_disp_super_ied_off(head, ior, 2);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1335

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1339

ior = nv50_disp_super_ior_arm(head);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1340

if (!ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1344

nv50_disp_super_ied_off(head, ior, 1);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1351

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1358

list_for_each_entry(ior, &disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1359

ior->func->state(ior, &ior->arm);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1360

ior->func->state(ior, &ior->asy);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1589

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

162

nv50_sor_bl_set(struct nvkm_ior *ior, int lvl)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

164

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

165

const u32 soff = nv50_ior_base(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

174

nv50_sor_bl_get(struct nvkm_ior *ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1757

ior = nvkm_ior_find(disp, SOR, ffs(outp->info.or) - 1);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1758

if (!WARN_ON(!ior))

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1759

ior->identity = true;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

176

struct nvkm_device *device = ior->disp->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

177

const u32 soff = nv50_ior_base(ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

94

nv50_pior_depth(struct nvkm_ior *ior, struct nvkm_ior_state *state, u32 ctrl)

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

99

if (state->head && state == &ior->asy) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

100

outp->ior = NULL;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

106

nvkm_outp_acquire_ior(struct nvkm_outp *outp, u8 user, struct nvkm_ior *ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

108

outp->ior = ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

109

outp->ior->asy.outp = outp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

110

outp->ior->asy.link = outp->info.sorconf.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

119

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

122

list_for_each_entry(ior, &outp->disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

123

if (!ior->identity && ior->hda == hda &&

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

124

!ior->asy.outp && ior->type == type && !ior->arm.outp &&

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

125

(ior->func->route.set || ior->id == __ffs(outp->info.or)))

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

126

return nvkm_outp_acquire_ior(outp, user, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

132

list_for_each_entry(ior, &outp->disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

133

if (!ior->identity && ior->hda == hda &&

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

134

!ior->asy.outp && ior->type == type &&

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

135

(ior->func->route.set || ior->id == __ffs(outp->info.or)))

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

136

return nvkm_outp_acquire_ior(outp, user, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

145

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

149

OUTP_TRACE(outp, "acquire %02x |= %02x %p", outp->acquired, user, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

150

if (ior) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

162

ior = nvkm_ior_find(outp->disp, SOR, ffs(outp->info.or) - 1);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

163

if (WARN_ON(!ior))

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

165

return nvkm_outp_acquire_ior(outp, user, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

171

list_for_each_entry(ior, &outp->disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

172

if (!ior->identity && !ior->asy.outp && ior->arm.outp == outp) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

184

WARN_ON(hda && !ior->hda);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

185

return nvkm_outp_acquire_ior(outp, user, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

219

if (outp->ior->func->bl)

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

220

ret = outp->ior->func->bl->set(outp->ior, level);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

237

if (outp->ior->func->bl)

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

238

ret = outp->ior->func->bl->get(outp->ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

294

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

304

ior = nvkm_ior_find(disp, type, -1);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

305

if (WARN_ON(!ior))

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

309

if (ior->func->route.get) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

310

id = ior->func->route.get(outp, &link);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

318

link = (ior->type == SOR) ? outp->info.sorconf.link : 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

321

ior = nvkm_ior_find(disp, type, id);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

322

if (WARN_ON(!ior))

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

325

return ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

333

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

337

ior = outp->func->inherit(outp);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

338

if (!ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

342

ior->func->state(ior, &ior->arm);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

343

if (!ior->arm.head || ior->arm.proto != proto) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

344

OUTP_DBG(outp, "no heads (%x %d %d)", ior->arm.head,

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

345

ior->arm.proto, proto);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

351

if (ior->func->route.get && !ior->arm.head && outp->info.type == DCB_OUTPUT_DP)

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

352

nvkm_dp_disable(outp, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

357

OUTP_DBG(outp, "on %s link %x", ior->name, ior->arm.link);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

358

ior->arm.outp = outp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

38

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

40

list_for_each_entry(ior, &disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

41

if ((outp = ior->arm.outp) && ior->arm.outp != ior->asy.outp) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

42

OUTP_DBG(outp, "release %s", ior->name);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

43

if (ior->func->route.set)

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

44

ior->func->route.set(outp, NULL);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

45

ior->arm.outp = NULL;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

49

list_for_each_entry(ior, &disp->iors, head) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

50

if ((outp = ior->asy.outp)) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

51

if (ior->asy.outp != ior->arm.outp) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

52

OUTP_DBG(outp, "acquire %s", ior->name);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

53

if (ior->func->route.set)

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

54

ior->func->route.set(outp, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

55

ior->arm.outp = ior->asy.outp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

94

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

95

OUTP_TRACE(outp, "release %02x &= %02x %p", outp->acquired, ~user, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

96

if (ior) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

99

outp->ior->asy.outp = NULL;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h

27

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

182

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

189

if (!ior->hda || !nvkm_head_find(outp->disp, args->v0.head))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

196

ior->func->dp->audio(ior, args->v0.head, true);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

198

if (ior->func->hdmi->audio)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

199

ior->func->hdmi->audio(ior, args->v0.head, true);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

201

ior->func->hda->hpd(ior, args->v0.head, true);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

202

ior->func->hda->eld(ior, args->v0.head, args->v0.data, argc);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

204

ior->func->hda->hpd(ior, args->v0.head, false);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

207

ior->func->dp->audio(ior, args->v0.head, false);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

209

if (ior->func->hdmi->audio)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

210

ior->func->hdmi->audio(ior, args->v0.head, false);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

219

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

228

switch (ior->func->hdmi ? args->v0.type : 0xff) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

230

ior->func->hdmi->infoframe_avi(ior, args->v0.head, &args->v0.data, size);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

233

ior->func->hdmi->infoframe_vsi(ior, args->v0.head, &args->v0.data, size);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

246

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

254

if (!ior->func->hdmi ||

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

257

(args->v0.scdc && !ior->func->hdmi->scdc))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

261

ior->func->hdmi->infoframe_avi(ior, args->v0.head, NULL, 0);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

262

ior->func->hdmi->infoframe_vsi(ior, args->v0.head, NULL, 0);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

263

ior->func->hdmi->ctrl(ior, args->v0.head, false, 0, 0);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

267

ior->func->hdmi->ctrl(ior, args->v0.head, args->v0.enable,

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

269

if (ior->func->hdmi->scdc)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

270

ior->func->hdmi->scdc(ior, args->v0.khz, args->v0.scdc, args->v0.scdc_scrambling,

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

337

if (!outp->ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

35

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

352

if (outp->ior && args->v0.type <= NVIF_OUTP_ACQUIRE_V0_PIOR)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

371

args->v0.or = outp->ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

372

args->v0.link = outp->ior->asy.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

380

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

387

ior = outp->func->inherit(outp);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

388

if (!ior || !ior->arm.head)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

397

if (ior->arm.proto != TMDS)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

40

if (!ior->func->dp || !ior->func->dp->vcpi || !nvkm_head_find(outp->disp, args->v0.head))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

401

if (ior->arm.proto != DP)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

405

if (ior->arm.proto != LVDS)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

409

if (ior->arm.proto != TV)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

413

if (ior->arm.proto != CRT)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

428

OUTP_TRACE(outp, "inherit %02x |= %02x %p", outp->acquired, NVKM_OUTP_USER, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

429

nvkm_outp_acquire_ior(outp, NVKM_OUTP_USER, ior);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

43

ior->func->dp->vcpi(ior, args->v0.head, args->v0.start_slot, args->v0.num_slots,

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

431

args->v0.or = ior->id;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

432

args->v0.link = ior->arm.link;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

433

args->v0.head = ffs(ior->arm.head) - 1;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

434

args->v0.proto = ior->arm.proto_evo;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

450

if (outp->ior->func->sense) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

451

ret = outp->ior->func->sense(outp->ior, args->v0.data);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

557

if (outp->ior)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

79

struct nvkm_ior *ior = outp->ior;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

84

if (!ior->func->dp || !nvkm_head_find(disp, args->v0.head))

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

86

if (!ior->func->dp->sst)

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

89

return ior->func->dp->sst(ior, args->v0.head,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

684

outp->disp->rm.assigned_sors &= ~BIT(outp->ior->id);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

685

outp->ior->asy.outp = NULL;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

686

outp->ior = NULL;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

693

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

726

ior = nvkm_ior_find(disp, SOR, or);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

727

if (WARN_ON(!ior))

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

730

nvkm_outp_acquire_ior(outp, NVKM_OUTP_USER, ior);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

777

struct nvkm_ior *ior;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

798

ior = nvkm_ior_find(disp, SOR, id);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

799

if (WARN_ON(!ior))

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

804

ior->arm.proto = TMDS;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

805

ior->arm.link = 1;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

808

ior->arm.proto = TMDS;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

809

ior->arm.link = 2;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

812

ior->arm.proto = TMDS;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

813

ior->arm.link = 3;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

816

ior->arm.proto = DP;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

817

ior->arm.link = 1;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

820

ior->arm.proto = DP;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

821

ior->arm.link = 2;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

828

ior->arm.proto_evo = proto;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

829

ior->arm.head = BIT(head->id);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

830

disp->rm.assigned_sors |= BIT(ior->id);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

831

return ior;

drivers/net/ethernet/davicom/dm9000.c

1059

int tx_status = ior(db, DM9000_NSR); /* Got TX status */

drivers/net/ethernet/davicom/dm9000.c

1098

ior(db, DM9000_MRCMDX); /* Dummy read */

drivers/net/ethernet/davicom/dm9000.c

1208

int_status = ior(db, DM9000_ISR); /* Got ISR */

drivers/net/ethernet/davicom/dm9000.c

1247

nsr = ior(db, DM9000_NSR);

drivers/net/ethernet/davicom/dm9000.c

1248

wcr = ior(db, DM9000_WCR);

drivers/net/ethernet/davicom/dm9000.c

1614

id_val = ior(db, DM9000_VIDL);

drivers/net/ethernet/davicom/dm9000.c

1615

id_val |= (u32)ior(db, DM9000_VIDH) << 8;

drivers/net/ethernet/davicom/dm9000.c

1616

id_val |= (u32)ior(db, DM9000_PIDL) << 16;

drivers/net/ethernet/davicom/dm9000.c

1617

id_val |= (u32)ior(db, DM9000_PIDH) << 24;

drivers/net/ethernet/davicom/dm9000.c

1632

id_val = ior(db, DM9000_CHIPR);

drivers/net/ethernet/davicom/dm9000.c

1685

addr[i] = ior(db, i + DM9000_PAR);

drivers/net/ethernet/davicom/dm9000.c

186

if (ior(db, DM9000_NCR) & 1)

drivers/net/ethernet/davicom/dm9000.c

192

if (ior(db, DM9000_NCR) & 1)

drivers/net/ethernet/davicom/dm9000.c

306

ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);

drivers/net/ethernet/davicom/dm9000.c

425

ret = ior(db, reg);

drivers/net/ethernet/davicom/dm9000.c

496

to[0] = ior(db, DM9000_EPDRL);

drivers/net/ethernet/davicom/dm9000.c

497

to[1] = ior(db, DM9000_EPDRH);

drivers/net/ethernet/davicom/dm9000.c

910

db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */

drivers/pinctrl/tegra/pinctrl-tegra114.c

1547

#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \

drivers/pinctrl/tegra/pinctrl-tegra114.c

1570

.ioreset_bit = PINGROUP_BIT_##ior(8), \

drivers/pinctrl/tegra/pinctrl-tegra124.c

1716

#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \

drivers/pinctrl/tegra/pinctrl-tegra124.c

1739

.ioreset_bit = PINGROUP_BIT_##ior(8), \

drivers/pinctrl/tegra/pinctrl-tegra30.c

2108

#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \

drivers/pinctrl/tegra/pinctrl-tegra30.c

2131

.ioreset_bit = PINGROUP_BIT_##ior(8), \