drivers/gpu/drm/nouveau/dispnv04/hw.c

300

ioread32_native(iovram + i * 4);

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

102

const u32 status = ioread32_native(&notifier->status);

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

94

return ioread32_native(&notifier->entries[idx].output_crc[0]);

drivers/gpu/drm/nouveau/dispnv50/crcc37d.c

79

return ioread32_native(crc_addr);

drivers/gpu/drm/nouveau/dispnv50/crcc37d.c

86

const u32 status = ioread32_native(&notifier->status);

drivers/gpu/drm/nouveau/include/nvif/object.h

56

#define nvif_rd32(a,b) ({ ((u32)nvif_rd((a), ioread32_native, 4, (b))); })

drivers/gpu/drm/nouveau/include/nvkm/core/device.h

127

#define nvkm_rd32(d,a) ioread32_native((d)->pri + (a))

drivers/gpu/drm/nouveau/nouveau_bo.c

822

return ioread32_native((void __force __iomem *)mem);

drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c

35

return ioread32_native(gpuobj->map + offset);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/bar.c

44

ioread32_native(bar->flushBAR2);

drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c

148

return ioread32_native(nv40_instmem(base)->iomem + addr);

drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c

58

return ioread32_native(iobj->imem->iomem + iobj->node->offset + offset);

drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c

111

return ioread32_native(nv50_instobj(memory)->map + offset);