CLK_DIVIDER_ONE_BASED
CLK_DIVIDER_ONE_BASED);
9, 7, CLK_DIVIDER_ONE_BASED);
CLK_DIVIDER_ONE_BASED);
base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED,
div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
div_hws->div.flags = CLK_DIVIDER_ONE_BASED |
if (flags & CLK_DIVIDER_ONE_BASED)
if (flags & CLK_DIVIDER_ONE_BASED)
if (flags & CLK_DIVIDER_ONE_BASED)
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST);
26, 4, NULL, 12, 0, CLK_DIVIDER_ONE_BASED);
14, 4, NULL, 10, 0, CLK_DIVIDER_ONE_BASED);
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST);
24, 7, NULL, 4, 1, CLK_DIVIDER_ONE_BASED);
CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
M_CFG_DIV(NULL, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
base + RCC_CFGR, 8, 6, CLK_DIVIDER_ONE_BASED |
div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;
.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED |
.flags = CLK_DIVIDER_ONE_BASED,
CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
.cfg.flags = CLK_DIVIDER_ONE_BASED,
priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED;
priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED;
priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED;
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0_lock},
{0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1_lock},
{0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock},
div->divider.flags = CLK_DIVIDER_ONE_BASED;
CLK_DIVIDER_ONE_BASED),
CLK_DIVIDER_ONE_BASED),
LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED),
if (flags & CLK_DIVIDER_ONE_BASED)
(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)
(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)
#define DEF_DIVFLAG (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO)
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
if (flags & CLK_DIVIDER_ONE_BASED)
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(16, 4, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(8, 4, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(4, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
.div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
CLK_DIVIDER_ONE_BASED);
CLK_DIVIDER_ONE_BASED);
CLK_DIVIDER_ONE_BASED);
if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
div->flags |= CLK_DIVIDER_ONE_BASED;
if (divider->flags & CLK_DIVIDER_ONE_BASED)
if (divider->flags & CLK_DIVIDER_ONE_BASED)
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
u8 divider_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
ccf_flag |= CLK_DIVIDER_ONE_BASED;
0, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);
4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);
pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
0, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);
4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);
data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0,
div->flags = CLK_DIVIDER_ONE_BASED;
nfc->nand_divider.flags = CLK_DIVIDER_ONE_BASED |