intel_uncore_rmw
val = intel_uncore_rmw(__to_uncore(display), reg, clear, set);
intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
intel_uncore_rmw(uncore,
intel_uncore_rmw(uncore,
intel_uncore_rmw(uncore,
intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
intel_uncore_rmw(uncore, EMR, 0, eir);
intel_uncore_rmw(uncore, XELPMP_RING_FAULT_REG,
intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID, 0);
intel_uncore_rmw(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID, 0);
intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0);
intel_uncore_rmw(gt->uncore, intel_gt_perf_limit_reasons_reg(gt),
intel_uncore_rmw(uncore,
intel_uncore_rmw(gt->uncore,
intel_uncore_rmw(gt->uncore,
intel_uncore_rmw(gt->uncore,
intel_uncore_rmw(uncore, MEMINTREN, MEMINT_EVAL_CHG_EN, 0);
intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0,
intel_uncore_rmw(uncore, GUC_SHIM_CONTROL2, 0, GUC_ENABLE_DEBUG_REG);
intel_uncore_rmw(gt->uncore,
intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit,
intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit,
r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit,
intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit,
intel_uncore_rmw(uncore, reg, clear, set);
misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0);
ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0);
intel_uncore_rmw(uncore, oastatus_reg,
intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
intel_uncore_rmw(uncore, GEN6_UCGCTL1,
intel_uncore_rmw(uncore, GEN6_UCGCTL1,
intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A),
misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0,
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6,
intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE,
intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,
intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE,
intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, ~VLV_GTLC_ALLOWWAKEREQ,
intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, ~VLV_GFX_CLK_FORCE_ON_BIT,
intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, VLV_GFX_CLK_FORCE_ON_BIT,
intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ,