intel_uncore_posting_read
intel_uncore_posting_read(__to_uncore(display), reg);
intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
intel_uncore_posting_read(uncore,
intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
intel_uncore_posting_read(uncore, reg);
intel_uncore_posting_read(uncore, ECR);
intel_uncore_posting_read(uncore, VIDSTART);
intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
intel_uncore_posting_read(uncore, fence_reg_lo);
intel_uncore_posting_read(uncore, fence_reg_lo);
intel_uncore_posting_read(uncore, reg);
intel_uncore_posting_read(uncore, reg);
intel_uncore_posting_read(uncore, regs.imr);
intel_uncore_posting_read(uncore, regs.emr);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_posting_read(uncore, regs.emr);
intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
intel_uncore_posting_read(&dev_priv->uncore, reg);
intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
intel_uncore_posting_read(uncore, regs.imr);
intel_uncore_posting_read(uncore, regs.iir);
intel_uncore_posting_read(uncore, regs.iir);
intel_uncore_posting_read(&dev_priv->uncore,
intel_uncore_posting_read(uncore, VLV_GTLC_WAKE_CTRL);