CLK_CON_PWM_IPCLKPORT_I_PCLK_S0
CLK_CON_PWM_IPCLKPORT_I_PCLK_S0,
CLK_CON_PWM_IPCLKPORT_I_PCLK_S0, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),