drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c

124

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c

126

imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;

drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c

127

imx_crtc_state->di_hsync_pin = 2;

drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c

128

imx_crtc_state->di_vsync_pin = 3;

drivers/gpu/drm/imx/ipuv3/imx-drm.h

18

static inline struct imx_crtc_state *to_imx_crtc_state(struct drm_crtc_state *s)

drivers/gpu/drm/imx/ipuv3/imx-drm.h

20

return container_of(s, struct imx_crtc_state, base);

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

313

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

325

imx_crtc_state->bus_flags = di->bus_flags;

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

329

imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

333

imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

339

imx_crtc_state->di_hsync_pin = 2;

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

340

imx_crtc_state->di_vsync_pin = 3;

drivers/gpu/drm/imx/ipuv3/imx-tve.c

298

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

drivers/gpu/drm/imx/ipuv3/imx-tve.c

301

imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;

drivers/gpu/drm/imx/ipuv3/imx-tve.c

302

imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;

drivers/gpu/drm/imx/ipuv3/imx-tve.c

303

imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

112

struct imx_crtc_state *state;

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

127

struct imx_crtc_state *state;

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

267

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

297

sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

299

sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

301

sig_cfg.bus_format = imx_crtc_state->bus_format;

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

303

sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

304

sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

319

imx_crtc_state->bus_format, sig_cfg.mode.hactive);

drivers/gpu/drm/imx/ipuv3/parallel-display.c

142

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

drivers/gpu/drm/imx/ipuv3/parallel-display.c

164

imx_crtc_state->bus_flags = bus_flags;

drivers/gpu/drm/imx/ipuv3/parallel-display.c

165

imx_crtc_state->bus_format = bridge_state->input_bus_cfg.format;

drivers/gpu/drm/imx/ipuv3/parallel-display.c

166

imx_crtc_state->di_hsync_pin = 2;

drivers/gpu/drm/imx/ipuv3/parallel-display.c

167

imx_crtc_state->di_vsync_pin = 3;