CLK_CON_MUX_MUX_CLK_CPUCL0_PLL
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),