intel_de_wait_for_set_ms
if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE, 50))
if (intel_de_wait_for_set_ms(display, TRANSCONF(display, dsi_trans),
if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
if (intel_de_wait_for_set_ms(display,
if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port),
if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),
ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),
if (intel_de_wait_for_set_ms(display,
if (intel_de_wait_for_set_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS,
if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL,
if (intel_de_wait_for_set_ms(display, regs->driver,
intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS,
if (intel_de_wait_for_set_ms(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))
if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))
if (intel_de_wait_for_set_ms(display, DPLL_STATUS, DPLL_LOCK(id), 5))
if (intel_de_wait_for_set_ms(display, enable_reg, PLL_POWER_STATE, 1))
if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 1))
ret = intel_de_wait_for_set_ms(display,
if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {
if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL,
if (intel_de_wait_for_set_ms(display,
if (intel_de_wait_for_set_ms(display,
ret = intel_de_wait_for_set_ms(display, HDCP_STATUS(display, cpu_transcoder, port),
if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
if (intel_de_wait_for_set_ms(display, PP_STATUS(display, 0), PP_ON, 5000))
if (intel_de_wait_for_set_ms(display, reg, TRANS_STATE_ENABLE, 100))
if (intel_de_wait_for_set_ms(display, LPT_TRANSCONF,
if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 5))
if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port),
if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port), mask, 100))
if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_set_ms(display, BXT_MIPI_PORT_CTRL(port),
if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display, port),
if (intel_de_wait_for_set_ms(display, BXT_DSI_PLL_ENABLE,