drivers/gpu/drm/i915/display/intel_cx0_phy.c

2232

val = intel_cx0_read(encoder, phy_lane_mask, PHY_CX0_TX_CONTROL(tx, 2));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2271

pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2273

pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2274

pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2589

serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2592

vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2597

vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_HDMI_RATE) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2895

cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

392

val = intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_H);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

394

val |= intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_L);

drivers/gpu/drm/i915/display/intel_cx0_phy.h

65

u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1026

return intel_cx0_read(encoder, lane_mask, addr);