CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK
CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK,
CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK, 2, CLK_SET_RATE_PARENT, 0),