drivers/gpu/drm/i915/gt/intel_engine_types.h

96

} indirect_ctx, per_ctx;

drivers/gpu/drm/i915/gt/intel_lrc.c

1568

GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size);

drivers/gpu/drm/i915/gt/intel_lrc.c

1842

&wa_ctx->indirect_ctx, &wa_ctx->per_ctx

drivers/gpu/drm/i915/gt/intel_lrc.c

881

if (wa_ctx->indirect_ctx.size) {

drivers/gpu/drm/i915/gt/intel_lrc.c

884

wa_ctx->indirect_ctx.offset,

drivers/gpu/drm/i915/gt/intel_lrc.c

885

wa_ctx->indirect_ctx.size);

drivers/gpu/drm/i915/gvt/cmd_parser.c

2895

if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2899

ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);

drivers/gpu/drm/i915/gvt/cmd_parser.c

2900

ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2902

gma_head = wa_ctx->indirect_ctx.guest_gma;

drivers/gpu/drm/i915/gvt/cmd_parser.c

2903

gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;

drivers/gpu/drm/i915/gvt/cmd_parser.c

2909

s.ring_start = wa_ctx->indirect_ctx.guest_gma;

drivers/gpu/drm/i915/gvt/cmd_parser.c

2913

s.rb_va = wa_ctx->indirect_ctx.shadow_va;

drivers/gpu/drm/i915/gvt/cmd_parser.c

2922

wa_ctx->indirect_ctx.guest_gma, ring_size);

drivers/gpu/drm/i915/gvt/cmd_parser.c

3007

int ctx_size = wa_ctx->indirect_ctx.size;

drivers/gpu/drm/i915/gvt/cmd_parser.c

3008

unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;

drivers/gpu/drm/i915/gvt/cmd_parser.c

3048

wa_ctx->indirect_ctx.obj = obj;

drivers/gpu/drm/i915/gvt/cmd_parser.c

3049

wa_ctx->indirect_ctx.shadow_va = map;

drivers/gpu/drm/i915/gvt/cmd_parser.c

3070

bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +

drivers/gpu/drm/i915/gvt/cmd_parser.c

3071

wa_ctx->indirect_ctx.size;

drivers/gpu/drm/i915/gvt/cmd_parser.c

3086

if (wa_ctx->indirect_ctx.size == 0)

drivers/gpu/drm/i915/gvt/scheduler.c

1645

u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;

drivers/gpu/drm/i915/gvt/scheduler.c

1716

RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);

drivers/gpu/drm/i915/gvt/scheduler.c

1718

workload->wa_ctx.indirect_ctx.guest_gma =

drivers/gpu/drm/i915/gvt/scheduler.c

1719

indirect_ctx & INDIRECT_CTX_ADDR_MASK;

drivers/gpu/drm/i915/gvt/scheduler.c

1720

workload->wa_ctx.indirect_ctx.size =

drivers/gpu/drm/i915/gvt/scheduler.c

1721

(indirect_ctx & INDIRECT_CTX_SIZE_MASK) *

drivers/gpu/drm/i915/gvt/scheduler.c

1724

if (workload->wa_ctx.indirect_ctx.size != 0) {

drivers/gpu/drm/i915/gvt/scheduler.c

1726

workload->wa_ctx.indirect_ctx.guest_gma,

drivers/gpu/drm/i915/gvt/scheduler.c

1727

workload->wa_ctx.indirect_ctx.size)) {

drivers/gpu/drm/i915/gvt/scheduler.c

1729

workload->wa_ctx.indirect_ctx.guest_gma);

drivers/gpu/drm/i915/gvt/scheduler.c

422

if (!wa_ctx->indirect_ctx.obj)

drivers/gpu/drm/i915/gvt/scheduler.c

425

i915_gem_object_lock(wa_ctx->indirect_ctx.obj, NULL);

drivers/gpu/drm/i915/gvt/scheduler.c

426

i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);

drivers/gpu/drm/i915/gvt/scheduler.c

427

i915_gem_object_unlock(wa_ctx->indirect_ctx.obj);

drivers/gpu/drm/i915/gvt/scheduler.c

428

i915_gem_object_put(wa_ctx->indirect_ctx.obj);

drivers/gpu/drm/i915/gvt/scheduler.c

430

wa_ctx->indirect_ctx.obj = NULL;

drivers/gpu/drm/i915/gvt/scheduler.c

431

wa_ctx->indirect_ctx.shadow_va = NULL;

drivers/gpu/drm/i915/gvt/scheduler.c

514

workload->wa_ctx.indirect_ctx.size) {

drivers/gpu/drm/i915/gvt/scheduler.c

612

(~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;

drivers/gpu/drm/i915/gvt/scheduler.c

619

(unsigned char *)wa_ctx->indirect_ctx.shadow_va +

drivers/gpu/drm/i915/gvt/scheduler.c

620

wa_ctx->indirect_ctx.size;

drivers/gpu/drm/i915/gvt/scheduler.c

624

if (wa_ctx->indirect_ctx.size == 0)

drivers/gpu/drm/i915/gvt/scheduler.c

629

i915_gem_object_lock(wa_ctx->indirect_ctx.obj, &ww);

drivers/gpu/drm/i915/gvt/scheduler.c

631

vma = i915_gem_object_ggtt_pin_ww(wa_ctx->indirect_ctx.obj, &ww, NULL,

drivers/gpu/drm/i915/gvt/scheduler.c

650

wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);

drivers/gpu/drm/i915/gvt/scheduler.h

80

struct shadow_indirect_ctx indirect_ctx;

drivers/mfd/intel-m10-bmc-pmci.c

386

struct indirect_ctx *ctx;

drivers/mfd/intel-m10-bmc-pmci.c

46

static int indirect_clear_cmd(struct indirect_ctx *ctx)

drivers/mfd/intel-m10-bmc-pmci.c

64

struct indirect_ctx *ctx = context;

drivers/mfd/intel-m10-bmc-pmci.c

96

struct indirect_ctx *ctx = context;