arch/powerpc/include/asm/eeh.h

415

u64 val = in_be64(addr);

arch/powerpc/include/asm/io.h

192

DEF_MMIO_IN_D(in_be64, 64, ld);

arch/powerpc/include/asm/io.h

197

return swab64(in_be64(addr));

arch/powerpc/include/asm/io.h

452

#define __do_readq_be(addr) in_be64(addr)

arch/powerpc/kvm/book3s_xive_native.c

40

val = in_be64(xd->eoi_mmio + offset);

arch/powerpc/platforms/cell/spufs/file.c

2470

mfc_control_RW = in_be64(&priv2->mfc_control_RW);

arch/powerpc/platforms/cell/spufs/hw_ops.c

141

tmp = in_be64(&priv2->spu_cfg_RW);

arch/powerpc/platforms/cell/spufs/hw_ops.c

152

return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);

arch/powerpc/platforms/cell/spufs/hw_ops.c

162

tmp = in_be64(&priv2->spu_cfg_RW);

arch/powerpc/platforms/cell/spufs/hw_ops.c

173

return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);

arch/powerpc/platforms/cell/spufs/hw_ops.c

92

*data = in_be64(&priv2->puint_mb_R);

arch/powerpc/platforms/cell/spufs/run.c

110

while ((in_be64(mfc_cntl) & MFC_CNTL_PURGE_DMA_STATUS_MASK)

arch/powerpc/platforms/cell/spufs/switch.c

1680

in_be64(&priv2->puint_mb_R);

arch/powerpc/platforms/cell/spufs/switch.c

174

switch (in_be64(&priv2->mfc_control_RW) &

arch/powerpc/platforms/cell/spufs/switch.c

177

POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &

arch/powerpc/platforms/cell/spufs/switch.c

184

in_be64(&priv2->mfc_control_RW) |

arch/powerpc/platforms/cell/spufs/switch.c

189

POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &

arch/powerpc/platforms/cell/spufs/switch.c

194

in_be64(&priv2->mfc_control_RW) &

arch/powerpc/platforms/cell/spufs/switch.c

260

csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;

arch/powerpc/platforms/cell/spufs/switch.c

304

POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);

arch/powerpc/platforms/cell/spufs/switch.c

342

if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {

arch/powerpc/platforms/cell/spufs/switch.c

345

in_be64(&priv2->puq[i].mfc_cq_data0_RW);

arch/powerpc/platforms/cell/spufs/switch.c

347

in_be64(&priv2->puq[i].mfc_cq_data1_RW);

arch/powerpc/platforms/cell/spufs/switch.c

349

in_be64(&priv2->puq[i].mfc_cq_data2_RW);

arch/powerpc/platforms/cell/spufs/switch.c

351

in_be64(&priv2->puq[i].mfc_cq_data3_RW);

arch/powerpc/platforms/cell/spufs/switch.c

355

in_be64(&priv2->spuq[i].mfc_cq_data0_RW);

arch/powerpc/platforms/cell/spufs/switch.c

357

in_be64(&priv2->spuq[i].mfc_cq_data1_RW);

arch/powerpc/platforms/cell/spufs/switch.c

359

in_be64(&priv2->spuq[i].mfc_cq_data2_RW);

arch/powerpc/platforms/cell/spufs/switch.c

361

in_be64(&priv2->spuq[i].mfc_cq_data3_RW);

arch/powerpc/platforms/cell/spufs/switch.c

410

in_be64(&priv2->spu_tag_status_query_RW);

arch/powerpc/platforms/cell/spufs/switch.c

421

csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);

arch/powerpc/platforms/cell/spufs/switch.c

422

csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);

arch/powerpc/platforms/cell/spufs/switch.c

433

csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);

arch/powerpc/platforms/cell/spufs/switch.c

478

POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &

arch/powerpc/platforms/cell/spufs/switch.c

518

csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);

arch/powerpc/platforms/cell/spufs/switch.c

540

csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);

arch/powerpc/platforms/cell/spufs/switch.c

562

csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);

arch/powerpc/platforms/cell/spufs/switch.c

612

csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);

arch/powerpc/platforms/cell/spufs/switch.c

626

csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);

arch/powerpc/platforms/cell/spufs/switch.c

633

csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);

arch/powerpc/platforms/cell/spufs/switch.c

634

csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);

arch/powerpc/platforms/cell/spufs/switch.c

651

csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);

arch/powerpc/platforms/cell/spufs/switch.c

653

csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);

arch/powerpc/platforms/cell/spufs/switch.c

668

csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);

arch/powerpc/platforms/cell/spufs/switch.c

984

POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &

arch/powerpc/platforms/powernv/eeh-powernv.c

119

*val = in_be64(phb->regs + offset);

arch/powerpc/platforms/powernv/ocxl.c

578

val = in_be64(arva + PNV_OCXL_ATSD_STAT);

arch/powerpc/platforms/powernv/ocxl.c

588

val = in_be64(arva + PNV_OCXL_ATSD_STAT);

arch/powerpc/platforms/powernv/rng.c

140

val = in_be64(rng->regs);

arch/powerpc/platforms/powernv/rng.c

90

*v = rng_whiten(rng, in_be64(rng->regs));

arch/powerpc/platforms/powernv/vas.h

475

return in_be64(win->hvwc_map+reg);

arch/powerpc/platforms/ps3/spu.c

367

while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)

arch/powerpc/platforms/ps3/spu.c

513

return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);

arch/powerpc/platforms/ps3/spu.c

523

return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);

arch/powerpc/sysdev/xive/common.c

227

val = in_be64(xd->eoi_mmio + offset);

arch/powerpc/sysdev/xive/native.c

403

in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);

arch/powerpc/sysdev/xive/native.c

440

in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);

drivers/dma/fsldma.h

203

#define fsl_ioread64be(p) in_be64(p)

drivers/misc/ocxl/link.c

112

*dsisr = in_be64(spa->reg_dsisr);

drivers/misc/ocxl/link.c

113

*dar = in_be64(spa->reg_dar);

drivers/misc/ocxl/link.c

114

reg = in_be64(spa->reg_pe_handle);

sound/ppc/snd_ps3.c

784

the_card.audio_irq_outlet = in_be64(mapped);