ADCX140_DRE_CFG0
{ ADCX140_DRE_CFG0, 0x7b },
regmap_reg_range(ADCX140_DSP_CFG0, ADCX140_DRE_CFG0),
SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,