img_ir_write
img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_status);
img_ir_write(priv, IMG_IR_IRQ_ENABLE, 0);
img_ir_write(priv, IMG_IR_LEAD_SYMB_TIMING, regs->ldr);
img_ir_write(priv, IMG_IR_S00_SYMB_TIMING, regs->s00);
img_ir_write(priv, IMG_IR_S01_SYMB_TIMING, regs->s01);
img_ir_write(priv, IMG_IR_S10_SYMB_TIMING, regs->s10);
img_ir_write(priv, IMG_IR_S11_SYMB_TIMING, regs->s11);
img_ir_write(priv, IMG_IR_FREE_SYMB_TIMING, ft);
img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_LW, (u32)filter->data);
img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_UP, (u32)(filter->data
img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, (u32)filter->mask);
img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, (u32)(filter->mask
img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, 0);
img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, 0);
img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_on);
img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en);
img_ir_write(priv, IMG_IR_CONTROL, 0);
img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en & IMG_IR_IRQ_EDGE);
img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_ALL & ~IMG_IR_IRQ_EDGE);
img_ir_write(priv, IMG_IR_STATUS, ir_status);
img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
img_ir_write(priv, IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_DATA_MATCH);
img_ir_write(priv, IMG_IR_IRQ_ENABLE,
img_ir_write(priv, IMG_IR_IRQ_ENABLE,
img_ir_write(priv, IMG_IR_CONTROL, 0);
img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
img_ir_write(priv, IMG_IR_CONTROL, 0);
img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
img_ir_write(priv, IMG_IR_IRQ_ENABLE,
img_ir_write(priv, IMG_IR_CONTROL, priv->hw.reg_timings.ctrl);
img_ir_write(priv, IMG_IR_CONTROL, 0);
img_ir_write(priv, IMG_IR_IRQ_ENABLE,
img_ir_write(priv, IMG_IR_STATUS, ir_status);
img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en);
img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_EDGE);
img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_EDGE);
img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en);